post on 27 Jan 2022 about 123362words need 412min
CC BY 4.0 （除特别声明或转载文章外）
如果这篇博客帮助到你，可以请我喝一杯咖啡~
近期一些工作需要对 GPU 进行仿真，需要使用到 GPGPU-Sim。鉴于相关中文资料较少且质量较低，此处给出一些自己的使用经验。
GPGPU-Sim 的安装有些复杂，因此我写了一个基于 spack 的安装脚本，可以通过以下方式引入。
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git clone https://github.com/SYSU-SCC/sysu-scc-spack-repo
spack repo add --scope=site sysu-scc-spack-repo
在我的使用过程发现，高于 [email protected] 的编译器编译出的 GPGPU-Sim 运行时会死循环，暂不知原因；GPGPU-Sim 依赖 GL，spack 默认安装的 mesa 会引入 llvm 的一长串依赖，需要很久的编译时间，可以去掉。
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spack install gpgpu-sim%[email protected] ^ mesa~llvm ^ [email protected]
spack load [email protected]
spack load gpgpu-sim
cd $(spack location -i gpgpu-sim)/gpgpu-sim_distribution
source setup_environment release
~/scal.cu用一个简单的向量乘法作为示例，同时记录每个线程执行的时钟周期数量。
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#include <cstdio>
#include <vector>
#include <cuda_runtime.h>
template <typename T>
__global__ void scal(
int n,
T alpha,
T *x,
int incx,
clock_t *clk = nullptr)
{
const auto id = blockDim.x * blockIdx.x + threadIdx.x;
auto beg = clock();
for (auto i_x = id; i_x < n; i_x += blockDim.x * gridDim.x)
x[i_x * incx] *= alpha;
auto end = clock();
if (clk != nullptr)
clk[id] = end - beg;
}
template <typename T>
struct wk_vector
{
T *device_data;
std::vector<T> host_data;
wk_vector(size_t n) : host_data(n)
{
cudaMalloc(&device_data, sizeof(T) * n);
}
~wk_vector() { cudaFree(device_data); }
void sync_device()
{
cudaMemcpy(
device_data,
host_data.data(),
sizeof(T) * host_data.size(),
cudaMemcpyHostToDevice);
}
void sync_host()
{
cudaMemcpy(
host_data.data(),
device_data,
sizeof(T) * host_data.size(),
cudaMemcpyDeviceToHost);
}
};
int main()
{
const int N = 97, GRID_DIM_X = 3, BLOCK_DIM_X = 64;
wk_vector<float> x(N);
x.host_data.assign(N, 1);
x.sync_device();
wk_vector<clock_t> clk(GRID_DIM_X * BLOCK_DIM_X);
clk.host_data.assign(clk.host_data.size(), -1);
clk.sync_device();
scal<float><<<GRID_DIM_X, BLOCK_DIM_X>>>(
N,
2,
x.device_data,
1,
clk.device_data);
clk.sync_host();
for (int i = 0; i < clk.host_data.size(); ++i)
std::printf(
"%s{ 'id' : %d, 'clk' : %d }\n",
i ? "," : "[",
i,
clk.host_data[i]);
printf("]"); // 按 json 格式打印
}
我的运行环境如下。
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$ nvidia-smi
Fri Jan 28 00:29:44 2022
+-----------------------------------------------------------------------------+
| NVIDIA-SMI 460.73.01 Driver Version: 460.73.01 CUDA Version: 11.2 |
|-------------------------------+----------------------+----------------------+
| GPU Name Persistence-M| Bus-Id Disp.A | Volatile Uncorr. ECC |
| Fan Temp Perf Pwr:Usage/Cap| Memory-Usage | GPU-Util Compute M. |
| | | MIG M. |
|===============================+======================+======================|
| 0 Tesla V100-SXM2... Off | 00000000:8A:00.0 Off | 0 |
| N/A 33C P0 37W / 300W | 0MiB / 16160MiB | 0% Default |
| | | N/A |
+-------------------------------+----------------------+----------------------+
| 1 Tesla V100-SXM2... Off | 00000000:8B:00.0 Off | 0 |
| N/A 32C P0 40W / 300W | 0MiB / 16160MiB | 0% Default |
| | | N/A |
+-------------------------------+----------------------+----------------------+
| 2 Tesla V100-SXM2... Off | 00000000:B3:00.0 Off | 0 |
| N/A 33C P0 41W / 300W | 0MiB / 16160MiB | 0% Default |
| | | N/A |
+-------------------------------+----------------------+----------------------+
| 3 Tesla V100-SXM2... Off | 00000000:B4:00.0 Off | 0 |
| N/A 34C P0 37W / 300W | 0MiB / 16160MiB | 0% Default |
| | | N/A |
+-------------------------------+----------------------+----------------------+
+-----------------------------------------------------------------------------+
| Processes: |
| GPU GI CI PID Type Process name GPU Memory |
| ID ID Usage |
|=============================================================================|
| No running processes found |
+-----------------------------------------------------------------------------+
编译运行。
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nvcc --cudart shared -arch=sm_70 -o ~/scal scal.cu
~/scal > real.log
以下是屏幕输出 real.log。
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[{ 'id' : 0, 'clk' : 834 }
,{ 'id' : 1, 'clk' : 834 }
,{ 'id' : 2, 'clk' : 834 }
,{ 'id' : 3, 'clk' : 834 }
,{ 'id' : 4, 'clk' : 834 }
,{ 'id' : 5, 'clk' : 834 }
,{ 'id' : 6, 'clk' : 834 }
,{ 'id' : 7, 'clk' : 834 }
,{ 'id' : 8, 'clk' : 834 }
,{ 'id' : 9, 'clk' : 834 }
,{ 'id' : 10, 'clk' : 834 }
,{ 'id' : 11, 'clk' : 834 }
,{ 'id' : 12, 'clk' : 834 }
,{ 'id' : 13, 'clk' : 834 }
,{ 'id' : 14, 'clk' : 834 }
,{ 'id' : 15, 'clk' : 834 }
,{ 'id' : 16, 'clk' : 834 }
,{ 'id' : 17, 'clk' : 834 }
,{ 'id' : 18, 'clk' : 834 }
,{ 'id' : 19, 'clk' : 834 }
,{ 'id' : 20, 'clk' : 834 }
,{ 'id' : 21, 'clk' : 834 }
,{ 'id' : 22, 'clk' : 834 }
,{ 'id' : 23, 'clk' : 834 }
,{ 'id' : 24, 'clk' : 834 }
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,{ 'id' : 32, 'clk' : 833 }
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,{ 'id' : 40, 'clk' : 833 }
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,{ 'id' : 42, 'clk' : 833 }
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,{ 'id' : 64, 'clk' : 825 }
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,{ 'id' : 96, 'clk' : 1017 }
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,{ 'id' : 124, 'clk' : 1017 }
,{ 'id' : 125, 'clk' : 1017 }
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,{ 'id' : 127, 'clk' : 1017 }
,{ 'id' : 128, 'clk' : 436 }
,{ 'id' : 129, 'clk' : 436 }
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,{ 'id' : 154, 'clk' : 436 }
,{ 'id' : 155, 'clk' : 436 }
,{ 'id' : 156, 'clk' : 436 }
,{ 'id' : 157, 'clk' : 436 }
,{ 'id' : 158, 'clk' : 436 }
,{ 'id' : 159, 'clk' : 436 }
,{ 'id' : 160, 'clk' : 436 }
,{ 'id' : 161, 'clk' : 436 }
,{ 'id' : 162, 'clk' : 436 }
,{ 'id' : 163, 'clk' : 436 }
,{ 'id' : 164, 'clk' : 436 }
,{ 'id' : 165, 'clk' : 436 }
,{ 'id' : 166, 'clk' : 436 }
,{ 'id' : 167, 'clk' : 436 }
,{ 'id' : 168, 'clk' : 436 }
,{ 'id' : 169, 'clk' : 436 }
,{ 'id' : 170, 'clk' : 436 }
,{ 'id' : 171, 'clk' : 436 }
,{ 'id' : 172, 'clk' : 436 }
,{ 'id' : 173, 'clk' : 436 }
,{ 'id' : 174, 'clk' : 436 }
,{ 'id' : 175, 'clk' : 436 }
,{ 'id' : 176, 'clk' : 436 }
,{ 'id' : 177, 'clk' : 436 }
,{ 'id' : 178, 'clk' : 436 }
,{ 'id' : 179, 'clk' : 436 }
,{ 'id' : 180, 'clk' : 436 }
,{ 'id' : 181, 'clk' : 436 }
,{ 'id' : 182, 'clk' : 436 }
,{ 'id' : 183, 'clk' : 436 }
,{ 'id' : 184, 'clk' : 436 }
,{ 'id' : 185, 'clk' : 436 }
,{ 'id' : 186, 'clk' : 436 }
,{ 'id' : 187, 'clk' : 436 }
,{ 'id' : 188, 'clk' : 436 }
,{ 'id' : 189, 'clk' : 436 }
,{ 'id' : 190, 'clk' : 436 }
,{ 'id' : 191, 'clk' : 436 }
]
拷贝仿真参数到工作目录下（假设是~），进行仿真。
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spack load gpgpu-sim
cd $(spack location -i gpgpu-sim)/gpgpu-sim_distribution
source setup_environment release
cp -r $(spack location -i gpgpu-sim)/gpgpu-sim_distribution/configs/tested-cfgs/SM7_QV100 ~
cd ~/SM7_QV100
LD_PRELOAD=$(spack location -i gpgpu-sim)/gpgpu-sim_distribution/lib/release/libcudart.so ~/scal > simulate.log
以下是屏幕输出 simulate.log，输出的运行周期数量与 real.log 相比差的不少。
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*** GPGPU-Sim Simulator Version 4.0.0 [build gpgpu-sim_git-commit-_modified_0.0] ***
GPGPU-Sim PTX: simulation mode 0 (can change with PTX_SIM_MODE_FUNC environment variable:
1=functional simulation only, 0=detailed performance simulator)
GPGPU-Sim PTX: overriding embedded ptx with ptx file (PTX_SIM_USE_PTX_FILE is set)
GPGPU-Sim: Configuration options:
-save_embedded_ptx 0 # saves ptx files embedded in binary as <n>.ptx
-keep 0 # keep intermediate files created by GPGPU-Sim when interfacing with external programs
-gpgpu_ptx_save_converted_ptxplus 0 # Saved converted ptxplus to a file
-gpgpu_occupancy_sm_number 70 # The SM number to pass to ptxas when getting register usage for computing GPU occupancy. This parameter is required in the config.
-ptx_opcode_latency_int 4,13,4,5,145,21 # Opcode latencies for integers <ADD,MAX,MUL,MAD,DIV,SHFL>Default 1,1,19,25,145,32
-ptx_opcode_latency_fp 4,13,4,5,39 # Opcode latencies for single precision floating points <ADD,MAX,MUL,MAD,DIV>Default 1,1,1,1,30
-ptx_opcode_latency_dp 8,19,8,8,330 # Opcode latencies for double precision floating points <ADD,MAX,MUL,MAD,DIV>Default 8,8,8,8,335
-ptx_opcode_latency_sfu 100 # Opcode latencies for SFU instructionsDefault 8
-ptx_opcode_latency_tesnor 64 # Opcode latencies for Tensor instructionsDefault 64
-ptx_opcode_initiation_int 2,2,2,2,8,4 # Opcode initiation intervals for integers <ADD,MAX,MUL,MAD,DIV,SHFL>Default 1,1,4,4,32,4
-ptx_opcode_initiation_fp 2,2,2,2,4 # Opcode initiation intervals for single precision floating points <ADD,MAX,MUL,MAD,DIV>Default 1,1,1,1,5
-ptx_opcode_initiation_dp 4,4,4,4,130 # Opcode initiation intervals for double precision floating points <ADD,MAX,MUL,MAD,DIV>Default 8,8,8,8,130
-ptx_opcode_initiation_sfu 8 # Opcode initiation intervals for sfu instructionsDefault 8
-ptx_opcode_initiation_tensor 64 # Opcode initiation intervals for tensor instructionsDefault 64
-cdp_latency 7200,8000,100,12000,1600 # CDP API latency <cudaStreamCreateWithFlags, cudaGetParameterBufferV2_init_perWarp, cudaGetParameterBufferV2_perKernel, cudaLaunchDeviceV2_init_perWarp, cudaLaunchDevicV2_perKernel>Default 7200,8000,100,12000,1600
-network_mode 2 # Interconnection network mode
-inter_config_file mesh # Interconnection network config file
-icnt_in_buffer_limit 512 # in_buffer_limit
-icnt_out_buffer_limit 512 # out_buffer_limit
-icnt_subnets 2 # subnets
-icnt_arbiter_algo 1 # arbiter_algo
-icnt_verbose 0 # inct_verbose
-icnt_grant_cycles 1 # grant_cycles
-gpgpu_ptx_use_cuobjdump 1 # Use cuobjdump to extract ptx and sass from binaries
-gpgpu_experimental_lib_support 0 # Try to extract code from cuda libraries [Broken because of unknown cudaGetExportTable]
-checkpoint_option 0 # checkpointing flag (0 = no checkpoint)
-checkpoint_kernel 1 # checkpointing during execution of which kernel (1- 1st kernel)
-checkpoint_CTA 0 # checkpointing after # of CTA (< less than total CTA)
-resume_option 0 # resume flag (0 = no resume)
-resume_kernel 0 # Resume from which kernel (1= 1st kernel)
-resume_CTA 0 # resume from which CTA
-checkpoint_CTA_t 0 # resume from which CTA
-checkpoint_insn_Y 0 # resume from which CTA
-gpgpu_ptx_convert_to_ptxplus 0 # Convert SASS (native ISA) to ptxplus and run ptxplus
-gpgpu_ptx_force_max_capability 70 # Force maximum compute capability
-gpgpu_ptx_inst_debug_to_file 0 # Dump executed instructions' debug information to file
-gpgpu_ptx_inst_debug_file inst_debug.txt # Executed instructions' debug output file
-gpgpu_ptx_inst_debug_thread_uid 1 # Thread UID for executed instructions' debug output
-gpgpu_simd_model 1 # 1 = post-dominator
-gpgpu_shader_core_pipeline 2048:32 # shader core pipeline config, i.e., {<nthread>:<warpsize>}
-gpgpu_tex_cache:l1 N:4:128:256,L:R:m:N:L,T:512:8,128:2 # per-shader L1 texture cache (READ-ONLY) config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>:<rf>}
-gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4 # per-shader L1 constant memory cache (READ-ONLY) config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>}
-gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4 # shader L1 instruction cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>}
-gpgpu_cache:dl1 S:1:128:256,L:L:s:N:L,A:256:8,16:0,32 # per-shader L1 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none}
-gpgpu_l1_banks 4 # The number of L1 cache banks
-gpgpu_l1_banks_byte_interleaving 32 # l1 banks byte interleaving granularity
-gpgpu_l1_banks_hashing_function 0 # l1 banks hashing function
-gpgpu_l1_latency 20 # L1 Hit Latency
-gpgpu_smem_latency 20 # smem Latency
-gpgpu_cache:dl1PrefL1 none # per-shader L1 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none}
-gpgpu_cache:dl1PrefShared none # per-shader L1 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none}
-gpgpu_gmem_skip_L1D 0 # global memory access skip L1D cache (implements -Xptxas -dlcm=cg, default=no skip)
-gpgpu_perfect_mem 0 # enable perfect memory mode (no cache miss)
-n_regfile_gating_group 4 # group of lanes that should be read/written together)
-gpgpu_clock_gated_reg_file 0 # enable clock gated reg file for power calculations
-gpgpu_clock_gated_lanes 0 # enable clock gated lanes for power calculations
-gpgpu_shader_registers 65536 # Number of registers per shader core. Limits number of concurrent CTAs. (default 8192)
-gpgpu_registers_per_block 65536 # Maximum number of registers per CTA. (default 8192)
-gpgpu_ignore_resources_limitation 0 # gpgpu_ignore_resources_limitation (default 0)
-gpgpu_shader_cta 32 # Maximum number of concurrent CTAs in shader (default 8)
-gpgpu_num_cta_barriers 16 # Maximum number of named barriers per CTA (default 16)
-gpgpu_n_clusters 80 # number of processing clusters
-gpgpu_n_cores_per_cluster 1 # number of simd cores per cluster
-gpgpu_n_cluster_ejection_buffer_size 32 # number of packets in ejection buffer
-gpgpu_n_ldst_response_buffer_size 2 # number of response packets in ld/st unit ejection buffer
-gpgpu_shmem_per_block 65536 # Size of shared memory per thread block or CTA (default 48kB)
-gpgpu_shmem_size 98304 # Size of shared memory per shader core (default 16kB)
-gpgpu_adaptive_cache_config 1 # adaptive_cache_config
-gpgpu_shmem_sizeDefault 98304 # Size of shared memory per shader core (default 16kB)
-gpgpu_shmem_size_PrefL1 16384 # Size of shared memory per shader core (default 16kB)
-gpgpu_shmem_size_PrefShared 16384 # Size of shared memory per shader core (default 16kB)
-gpgpu_shmem_num_banks 32 # Number of banks in the shared memory in each shader core (default 16)
-gpgpu_shmem_limited_broadcast 0 # Limit shared memory to do one broadcast per cycle (default on)
-gpgpu_shmem_warp_parts 1 # Number of portions a warp is divided into for shared memory bank conflict check
-gpgpu_mem_unit_ports 1 # The number of memory transactions allowed per core cycle
-gpgpu_shmem_warp_parts 1 # Number of portions a warp is divided into for shared memory bank conflict check
-gpgpu_warpdistro_shader -1 # Specify which shader core to collect the warp size distribution from
-gpgpu_warp_issue_shader 0 # Specify which shader core to collect the warp issue distribution from
-gpgpu_local_mem_map 1 # Mapping from local memory space address to simulated GPU physical address space (default = enabled)
-gpgpu_num_reg_banks 16 # Number of register banks (default = 8)
-gpgpu_reg_bank_use_warp_id 0 # Use warp ID in mapping registers to banks (default = off)
-gpgpu_sub_core_model 1 # Sub Core Volta/Pascal model (default = off)
-gpgpu_enable_specialized_operand_collector 0 # enable_specialized_operand_collector
-gpgpu_operand_collector_num_units_sp 4 # number of collector units (default = 4)
-gpgpu_operand_collector_num_units_dp 0 # number of collector units (default = 0)
-gpgpu_operand_collector_num_units_sfu 4 # number of collector units (default = 4)
-gpgpu_operand_collector_num_units_int 0 # number of collector units (default = 0)
-gpgpu_operand_collector_num_units_tensor_core 4 # number of collector units (default = 4)
-gpgpu_operand_collector_num_units_mem 2 # number of collector units (default = 2)
-gpgpu_operand_collector_num_units_gen 8 # number of collector units (default = 0)
-gpgpu_operand_collector_num_in_ports_sp 1 # number of collector unit in ports (default = 1)
-gpgpu_operand_collector_num_in_ports_dp 0 # number of collector unit in ports (default = 0)
-gpgpu_operand_collector_num_in_ports_sfu 1 # number of collector unit in ports (default = 1)
-gpgpu_operand_collector_num_in_ports_int 0 # number of collector unit in ports (default = 0)
-gpgpu_operand_collector_num_in_ports_tensor_core 1 # number of collector unit in ports (default = 1)
-gpgpu_operand_collector_num_in_ports_mem 1 # number of collector unit in ports (default = 1)
-gpgpu_operand_collector_num_in_ports_gen 8 # number of collector unit in ports (default = 0)
-gpgpu_operand_collector_num_out_ports_sp 1 # number of collector unit in ports (default = 1)
-gpgpu_operand_collector_num_out_ports_dp 0 # number of collector unit in ports (default = 0)
-gpgpu_operand_collector_num_out_ports_sfu 1 # number of collector unit in ports (default = 1)
-gpgpu_operand_collector_num_out_ports_int 0 # number of collector unit in ports (default = 0)
-gpgpu_operand_collector_num_out_ports_tensor_core 1 # number of collector unit in ports (default = 1)
-gpgpu_operand_collector_num_out_ports_mem 1 # number of collector unit in ports (default = 1)
-gpgpu_operand_collector_num_out_ports_gen 8 # number of collector unit in ports (default = 0)
-gpgpu_coalesce_arch 60 # Coalescing arch (GT200 = 13, Fermi = 20)
-gpgpu_num_sched_per_core 4 # Number of warp schedulers per core
-gpgpu_max_insn_issue_per_warp 1 # Max number of instructions that can be issued per warp in one cycle by scheduler (either 1 or 2)
-gpgpu_dual_issue_diff_exec_units 1 # should dual issue use two different execution unit resources (Default = 1)
-gpgpu_simt_core_sim_order 1 # Select the simulation order of cores in a cluster (0=Fix, 1=Round-Robin)
-gpgpu_pipeline_widths 4,4,4,4,4,4,4,4,4,4,8,4,4 # Pipeline widths ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_INT,OC_EX_SFU,OC_EX_MEM,EX_WB,ID_OC_TENSOR_CORE,OC_EX_TENSOR_CORE
-gpgpu_tensor_core_avail 1 # Tensor Core Available (default=0)
-gpgpu_num_sp_units 4 # Number of SP units (default=1)
-gpgpu_num_dp_units 4 # Number of DP units (default=0)
-gpgpu_num_int_units 4 # Number of INT units (default=0)
-gpgpu_num_sfu_units 4 # Number of SF units (default=1)
-gpgpu_num_tensor_core_units 4 # Number of tensor_core units (default=1)
-gpgpu_num_mem_units 1 # Number if ldst units (default=1) WARNING: not hooked up to anything
-gpgpu_scheduler gto # Scheduler configuration: < lrr | gto | two_level_active > If two_level_active:<num_active_warps>:<inner_prioritization>:<outer_prioritization>For complete list of prioritization values see shader.h enum scheduler_prioritization_typeDefault: gto
-gpgpu_concurrent_kernel_sm 0 # Support concurrent kernels on a SM (default = disabled)
-gpgpu_perfect_inst_const_cache 1 # perfect inst and const cache mode, so all inst and const hits in the cache(default = disabled)
-gpgpu_inst_fetch_throughput 4 # the number of fetched intruction per warp each cycle
-gpgpu_reg_file_port_throughput 2 # the number ports of the register file
-specialized_unit_1 0,4,4,4,4,BRA # specialized unit config {<enabled>,<num_units>:<latency>:<initiation>,<ID_OC_SPEC>:<OC_EX_SPEC>,<NAME>}
-specialized_unit_2 0,4,4,4,4,BRA # specialized unit config {<enabled>,<num_units>:<latency>:<initiation>,<ID_OC_SPEC>:<OC_EX_SPEC>,<NAME>}
-specialized_unit_3 0,4,4,4,4,BRA # specialized unit config {<enabled>,<num_units>:<latency>:<initiation>,<ID_OC_SPEC>:<OC_EX_SPEC>,<NAME>}
-specialized_unit_4 0,4,4,4,4,BRA # specialized unit config {<enabled>,<num_units>:<latency>:<initiation>,<ID_OC_SPEC>:<OC_EX_SPEC>,<NAME>}
-specialized_unit_5 0,4,4,4,4,BRA # specialized unit config {<enabled>,<num_units>:<latency>:<initiation>,<ID_OC_SPEC>:<OC_EX_SPEC>,<NAME>}
-specialized_unit_6 0,4,4,4,4,BRA # specialized unit config {<enabled>,<num_units>:<latency>:<initiation>,<ID_OC_SPEC>:<OC_EX_SPEC>,<NAME>}
-specialized_unit_7 0,4,4,4,4,BRA # specialized unit config {<enabled>,<num_units>:<latency>:<initiation>,<ID_OC_SPEC>:<OC_EX_SPEC>,<NAME>}
-specialized_unit_8 0,4,4,4,4,BRA # specialized unit config {<enabled>,<num_units>:<latency>:<initiation>,<ID_OC_SPEC>:<OC_EX_SPEC>,<NAME>}
-gpgpu_perf_sim_memcpy 1 # Fill the L2 cache on memcpy
-gpgpu_simple_dram_model 0 # simple_dram_model with fixed latency and BW
-gpgpu_dram_scheduler 1 # 0 = fifo, 1 = FR-FCFS (defaul)
-gpgpu_dram_partition_queues 64:64:64:64 # i2$:$2d:d2$:$2i
-l2_ideal 0 # Use a ideal L2 cache that always hit
-gpgpu_cache:dl2 S:32:128:24,L:B:m:L:P,A:192:4,32:0,32 # unified banked L2 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>}
-gpgpu_cache:dl2_texture_only 0 # L2 cache used for texture only
-gpgpu_n_mem 32 # number of memory modules (e.g. memory controllers) in gpu
-gpgpu_n_sub_partition_per_mchannel 2 # number of memory subpartition in each memory module
-gpgpu_n_mem_per_ctrlr 1 # number of memory chips per memory controller
-gpgpu_memlatency_stat 14 # track and display latency statistics 0x2 enables MC, 0x4 enables queue logs
-gpgpu_frfcfs_dram_sched_queue_size 64 # 0 = unlimited (default); # entries per chip
-gpgpu_dram_return_queue_size 192 # 0 = unlimited (default); # entries per chip
-gpgpu_dram_buswidth 16 # default = 4 bytes (8 bytes per cycle at DDR)
-gpgpu_dram_burst_length 2 # Burst length of each DRAM request (default = 4 data bus cycle)
-dram_data_command_freq_ratio 2 # Frequency ratio between DRAM data bus and command bus (default = 2 times, i.e. DDR)
-gpgpu_dram_timing_opt nbk=16:CCD=1:RRD=3:RCD=12:RAS=28:RP=12:RC=40: CL=12:WL=2:CDLR=3:WR=10:nbkgrp=4:CCDL=2:RTPL=3 # DRAM timing parameters = {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL}
-gpgpu_l2_rop0a1a746f03c3abbded97bceebafceee7 /GPUFS/sysu_hpcedu_302/asc21/wuk/scal
Extracting PTX file and ptxas options 1: scal.1.sm_70.ptx -arch=sm_70
_latency 160 # ROP queue latency (default 85)
-dram_latency 100 # DRAM latency (default 30)
-dram_dual_bus_interface 1 # dual_bus_interface (default = 0)
-dram_bnk_indexing_policy 0 # dram_bnk_indexing_policy (0 = normal indexing, 1 = Xoring with the higher bits) (Default = 0)
-dram_bnkgrp_indexing_policy 1 # dram_bnkgrp_indexing_policy (0 = take higher bits, 1 = take lower bits) (Default = 0)
-dram_seperate_write_queue_enable 0 # Seperate_Write_Queue_Enable
-dram_write_queue_size 32:28:16 # Write_Queue_Size
-dram_elimnate_rw_turnaround 0 # elimnate_rw_turnaround i.e set tWTR and tRTW = 0
-icnt_flit_size 40 # icnt_flit_size
-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCB.CCCSSSSS # mapping memory address to dram model {dramid@<start bit>;<memory address map>}
-gpgpu_mem_addr_test 0 # run sweep test to check address mapping for aliased address
-gpgpu_mem_address_mask 1 # 0 = old addressing mask, 1 = new addressing mask, 2 = new add. mask + flipped bank sel and chip sel bits
-gpgpu_memory_partition_indexing 2 # 0 = no indexing, 1 = bitwise xoring, 2 = IPoly, 3 = custom indexing
-gpuwattch_xml_file gpuwattch.xml # GPUWattch XML file
-power_simulation_enabled 0 # Turn on power simulator (1=On, 0=Off)
-power_per_cycle_dump 0 # Dump detailed power output each cycle
-power_trace_enabled 0 # produce a file for the power trace (1=On, 0=Off)
-power_trace_zlevel 6 # Compression level of the power trace output log (0=no comp, 9=highest)
-steady_power_levels_enabled 0 # produce a file for the steady power levels (1=On, 0=Off)
-steady_state_definition 8:4 # allowed deviation:number of samples
-gpgpu_max_cycle 0 # terminates gpu simulation early (0 = no limit)
-gpgpu_max_insn 0 # terminates gpu simulation early (0 = no limit)
-gpgpu_max_cta 0 # terminates gpu simulation early (0 = no limit)
-gpgpu_max_completed_cta 0 # terminates gpu simulation early (0 = no limit)
-gpgpu_runtime_stat 500 # display runtime statistics such as dram utilization {<freq>:<flag>}
-liveness_message_freq 1 # Minimum number of seconds between simulation liveness messages (0 = always print)
-gpgpu_compute_capability_major 7 # Major compute capability version number
-gpgpu_compute_capability_minor 0 # Minor compute capability version number
-gpgpu_flush_l1_cache 1 # Flush L1 cache at the end of each kernel call
-gpgpu_flush_l2_cache 0 # Flush L2 cache at the end of each kernel call
-gpgpu_deadlock_detect 1 # Stop the simulation at deadlock (1=on (default), 0=off)
-gpgpu_ptx_instruction_classification 0 # if enabled will classify ptx instruction types per kernel (Max 255 kernels now)
-gpgpu_ptx_sim_mode 0 # Select between Performance (default) or Functional simulation (1)
-gpgpu_clock_domains 1132.0:1132.0:1132.0:850.0 # Clock Domain Frequencies in MhZ {<Core Clock>:<ICNT Clock>:<L2 Clock>:<DRAM Clock>}
-gpgpu_max_concurrent_kernel 8 # maximum kernels that can run concurrently on GPU
-gpgpu_cflog_interval 0 # Interval between each snapshot in control flow logger
-visualizer_enabled 0 # Turn on visualizer output (1=On, 0=Off)
-visualizer_outputfile NULL # Specifies the output log file for visualizer
-visualizer_zlevel 6 # Compression level of the visualizer output log (0=no comp, 9=highest)
-gpgpu_stack_size_limit 1024 # GPU thread stack size
-gpgpu_heap_size_limit 8388608 # GPU malloc heap size
-gpgpu_runtime_sync_depth_limit 2 # GPU device runtime synchronize depth
-gpgpu_runtime_pending_launch_count_limit 2048 # GPU device runtime pending launch count
-trace_enabled 0 # Turn on traces
-trace_components none # comma seperated list of traces to enable. Complete list found in trace_streams.tup. Default none
-trace_sampling_core 0 # The core which is printed using CORE_DPRINTF. Default 0
-trace_sampling_memory_partition -1 # The memory partition which is printed using MEMPART_DPRINTF. Default -1 (i.e. all)
-enable_ptx_file_line_stats 1 # Turn on PTX source line statistic profiling. (1 = On)
-ptx_line_stats_filename gpgpu_inst_stats.txt # Output file for PTX source line statistics.
-gpgpu_kernel_launch_latency 5000 # Kernel launch latency in cycles. Default: 0
-gpgpu_cdp_enabled 0 # Turn on CDP
-gpgpu_TB_launch_latency 0 # thread block launch latency in cycles. Default: 0
DRAM Timing Options:
nbk 16 # number of banks
CCD 1 # column to column delay
RRD 3 # minimal delay between activation of rows in different banks
RCD 12 # row to column delay
RAS 28 # time needed to activate row
RP 12 # time needed to precharge (deactivate) row
RC 40 # row cycle time
CDLR 3 # switching from write to read (changes tWTR)
WR 10 # last data-in to row precharge
CL 12 # CAS latency
WL 2 # Write latency
nbkgrp 4 # number of bank groups
CCDL 2 # column to column delay between accesses to different bank groups
RTPL 3 # read to precharge delay between accesses to different bank groups
Total number of memory sub partition = 64
addr_dec_mask[CHIP] = 0000000000001f00 high:13 low:8
addr_dec_mask[BK] = 00000000000e2000 high:20 low:13
addr_dec_mask[ROW] = 00000001fff00000 high:33 low:20
addr_dec_mask[COL] = 000000000001c0ff high:17 low:0
addr_dec_mask[BURST] = 000000000000001f high:5 low:0
sub_partition_id_mask = 0000000000002000
GPGPU-Sim uArch: clock freqs: 1132000000.000000:1132000000.000000:1132000000.000000:850000000.000000
GPGPU-Sim uArch: clock periods: 0.00000000088339222615:0.00000000088339222615:0.00000000088339222615:0.00000000117647058824
*** Initializing Memory Statistics ***
GPGPU-Sim uArch: performance model initialization complete.
self exe links to: /GPUFS/sysu_hpcedu_302/asc21/wuk/scal
self exe links to: /GPUFS/sysu_hpcedu_302/asc21/wuk/scal
11.0
GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 1, filename=default
self exe links to: /GPUFS/sysu_hpcedu_302/asc21/wuk/scal
Running md5sum using "md5sum /GPUFS/sysu_hpcedu_302/asc21/wuk/scal "
self exe links to: /GPUFS/sysu_hpcedu_302/asc21/wuk/scal
Extracting specific PTX file named scal.1.sm_70.ptx
GPGPU-Sim PTX: __cudaRegisterFunction _Z4scalIfEviT_PS0_iPl : hostFun 0x0x401567, fat_cubin_handle = 1
GPGPU-Sim PTX: Parsing scal.1.sm_70.ptx
GPGPU-Sim PTX: instruction assembly for function '_Z4scalIfEviT_PS0_iPl'... done.
GPGPU-Sim PTX: finished parsing EMBEDDED .ptx file scal.1.sm_70.ptx
GPGPU-Sim PTX: loading globals with explicit initializers...
GPGPU-Sim PTX: finished loading globals (0 bytes total).
GPGPU-Sim PTX: loading constants with explicit initializers... done.
GPGPU-Sim PTX: Loading PTXInfo from scal.1.sm_70.ptx
GPGPU-Sim PTX: Kernel '_Z4scalIfEviT_PS0_iPl' : regs=11, lmem=0, smem=0, cmem=384
GPGPU-Sim PTX: Setting up arguments for 4 bytes starting at 0x7fffca6b335c..
GPGPU-Sim PTX: Setting up arguments for 4 bytes starting at 0x7fffca6b3358..
GPGPU-Sim PTX: Setting up arguments for 8 bytes starting at 0x7fffca6b3350..
GPGPU-Sim PTX: Setting up arguments for 4 bytes starting at 0x7fffca6b334c..
GPGPU-Sim PTX: Setting up arguments for 8 bytes starting at 0x7fffca6b3340..
GPGPU-Sim PTX: cudaLaunch for 0x0x401567 (mode=performance simulation) on stream 0
GPGPU-Sim PTX: finding reconvergence points for '_Z4scalIfEviT_PS0_iPl'...
GPGPU-Sim PTX: Finding dominators for '_Z4scalIfEviT_PS0_iPl'...
GPGPU-Sim PTX: Finding immediate dominators for '_Z4scalIfEviT_PS0_iPl'...
GPGPU-Sim PTX: Finding postdominators for '_Z4scalIfEviT_PS0_iPl'...
GPGPU-Sim PTX: Finding immediate postdominators for '_Z4scalIfEviT_PS0_iPl'...
GPGPU-Sim PTX: pre-decoding instructions for '_Z4scalIfEviT_PS0_iPl'...
GPGPU-Sim PTX: reconvergence points for _Z4scalIfEviT_PS0_iPl...
GPGPU-Sim PTX: 1 (potential) branch divergence @ PC=0x058 (scal.1.sm_70.ptx:42) @%p1 bra BB0_3;
GPGPU-Sim PTX: immediate post dominator @ PC=0x0c8 (scal.1.sm_70.ptx:62) mov.u32 %r15, %clock;
GPGPU-Sim PTX: 2 (potential) branch divergence @ PC=0x0c0 (scal.1.sm_70.ptx:58) @%p2 bra BB0_2;
GPGPU-Sim PTX: immediate post dominator @ PC=0x0c8 (scal.1.sm_70.ptx:62) mov.u32 %r15, %clock;
GPGPU-Sim PTX: 3 (potential) branch divergence @ PC=0x0d8 (scal.1.sm_70.ptx:65) @%p3 bra BB0_5;
GPGPU-Sim PTX: immediate post dominator @ PC=0x118 (scal.1.sm_70.ptx:76) ret;
GPGPU-Sim PTX: ... end of reconvergence points for _Z4scalIfEviT_PS0_iPl
GPGPU-Sim PTX: ... done pre-decoding instructions for '_Z4scalIfEviT_PS0_iPl'.
GPGPU-Sim PTX: pushing kernel '_Z4scalIfEviT_PS0_iPl' to stream 0, gridDim= (3,1,1) blockDim = (64,1,1)
GPGPU-Sim uArch: Shader 0 bind to kernel 1 '_Z4scalIfEviT_PS0_iPl'
GPGPU-Sim uArch: CTA/core = 32, limited by: threads cta_limit
GPGPU-Sim: Reconfigure L1 cache to 128KB
GPGPU-Sim uArch: Shader 1 bind to kernel 1 '_Z4scalIfEviT_PS0_iPl'
GPGPU-Sim uArch: Shader 2 bind to kernel 1 '_Z4scalIfEviT_PS0_iPl'
Destroy streams for kernel 1: size 0
kernel_name = _Z4scalIfEviT_PS0_iPl
kernel_launch_uid = 1
gpu_sim_cycle = 5533
gpu_sim_insn = 5291
gpu_ipc = 0.9563
gpu_tot_sim_cycle = 5533
gpu_tot_sim_insn = 5291
gpu_tot_ipc = 0.9563
gpu_tot_issued_cta = 3
gpu_occupancy = 3.0969%
gpu_tot_occupancy = 3.0969%
max_total_param_size = 0
gpu_stall_dramfull = 0
gpu_stall_icnt2sh = 0
partiton_level_parallism = 0.0134
partiton_level_parallism_total = 0.0134
partiton_level_parallism_util = 1.8500
partiton_level_parallism_util_total = 1.8500
L2_BW = 0.4845 GB/Sec
L2_BW_total = 0.4845 GB/Sec
gpu_total_sim_rate=1763
========= Core cache stats =========
L1I_cache:
L1I_total_cache_accesses = 0
L1I_total_cache_misses = 0
L1I_total_cache_pending_hits = 0
L1I_total_cache_reservation_fails = 0
L1D_cache:
L1D_cache_core[0]: Access = 32, Miss = 24, Miss_rate = 0.750, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[1]: Access = 26, Miss = 21, Miss_rate = 0.808, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[2]: Access = 16, Miss = 16, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[28]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[29]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[30]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[31]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[32]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[33]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[34]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[35]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[36]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[37]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[38]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[39]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[40]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[41]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[42]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[43]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[44]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[45]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[46]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[47]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[48]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[49]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[50]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[51]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[52]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[53]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[54]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[55]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[56]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[57]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[58]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[59]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[60]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[61]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[62]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[63]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[64]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[65]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[66]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[67]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[68]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[69]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[70]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[71]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[72]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[73]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[74]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[75]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[76]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[77]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[78]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[79]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_total_cache_accesses = 74
L1D_total_cache_misses = 61
L1D_total_cache_miss_rate = 0.8243
L1D_total_cache_pending_hits = 0
L1D_total_cache_reservation_fails = 0
L1D_cache_data_port_util = 0.010
L1D_cache_fill_port_util = 0.010
L1C_cache:
L1C_total_cache_accesses = 0
L1C_total_cache_misses = 0
L1C_total_cache_pending_hits = 0
L1C_total_cache_reservation_fails = 0
L1T_cache:
L1T_total_cache_accesses = 0
L1T_total_cache_misses = 0
L1T_total_cache_pending_hits = 0
L1T_total_cache_reservation_fails = 0
Total_core_cache_stats:
Total_core_cache_stats_breakdown[GLOBAL_ACC_R][HIT] = 0
Total_core_cache_stats_breakdown[GLOBAL_ACC_R][HIT_RESERVED] = 0
Total_core_cache_stats_breakdown[GLOBAL_ACC_R][MISS] = 13
Total_core_cache_stats_breakdown[GLOBAL_ACC_R][RESERVATION_FAIL] = 0
Total_core_cache_stats_breakdown[GLOBAL_ACC_R][SECTOR_MISS] = 0
Total_core_cache_stats_breakdown[LOCAL_ACC_R][HIT] = 0
Total_core_cache_stats_breakdown[LOCAL_ACC_R][HIT_RESERVED] = 0
Total_core_cache_stats_breakdown[LOCAL_ACC_R][MISS] = 0
Total_core_cache_stats_breakdown[LOCAL_ACC_R][RESERVATION_FAIL] = 0
Total_core_cache_stats_breakdown[LOCAL_ACC_R][SECTOR_MISS] = 0
Total_core_cache_stats_breakdown[CONST_ACC_R][HIT] = 0
Total_core_cache_stats_breakdown[CONST_ACC_R][HIT_RESERVED] = 0
Total_core_cache_stats_breakdown[CONST_ACC_R][MISS] = 0
Total_core_cache_stats_breakdown[CONST_ACC_R][RESERVATION_FAIL] = 0
Total_core_cache_stats_breakdown[CONST_ACC_R][SECTOR_MISS] = 0
Total_core_cache_stats_breakdown[TEXTURE_ACC_R][HIT] = 0
Total_core_cache_stats_breakdown[TEXTURE_ACC_R][HIT_RESERVED] = 0
Total_core_cache_stats_breakdown[TEXTURE_ACC_R][MISS] = 0
Total_core_cache_stats_breakdown[TEXTURE_ACC_R][RESERVATION_FAIL] = 0
Total_core_cache_stats_breakdown[TEXTURE_ACC_R][SECTOR_MISS] = 0
Total_core_cache_stats_breakdown[GLOBAL_ACC_W][HIT] = 13
Total_core_cache_stats_breakdown[GLOBAL_ACC_W][HIT_RESERVED] = 0
Total_core_cache_stats_breakdown[GLOBAL_ACC_W][MISS] = 48
Total_core_cache_stats_breakdown[GLOBAL_ACC_W][RESERVATION_FAIL] = 0
Total_core_cache_stats_breakdown[GLOBAL_ACC_W][SECTOR_MISS] = 0
Total_core_cache_stats_breakdown[LOCAL_ACC_W][HIT] = 0
Total_core_cache_stats_breakdown[LOCAL_ACC_W][HIT_RESERVED] = 0
Total_core_cache_stats_breakdown[LOCAL_ACC_W][MISS] = 0
Total_core_cache_stats_breakdown[LOCAL_ACC_W][RESERVATION_FAIL] = 0
Total_core_cache_stats_breakdown[LOCAL_ACC_W][SECTOR_MISS] = 0
Total_core_cache_stats_breakdown[L1_WRBK_ACC][HIT] = 0
Total_core_cache_stats_breakdown[L1_WRBK_ACC][HIT_RESERVED] = 0
Total_core_cache_stats_breakdown[L1_WRBK_ACC][MISS] = 0
Total_core_cache_stats_breakdown[L1_WRBK_ACC][RESERVATION_FAIL] = 0
Total_core_cache_stats_breakdown[L1_WRBK_ACC][SECTOR_MISS] = 0
Total_core_cache_stats_breakdown[L2_WRBK_ACC][HIT] = 0
Total_core_cache_stats_breakdown[L2_WRBK_ACC][HIT_RESERVED] = 0
Total_core_cache_stats_breakdown[L2_WRBK_ACC][MISS] = 0
Total_core_cache_stats_breakdown[L2_WRBK_ACC][RESERVATION_FAIL] = 0
Total_core_cache_stats_breakdown[L2_WRBK_ACC][SECTOR_MISS] = 0
Total_core_cache_stats_breakdown[INST_ACC_R][HIT] = 0
Total_core_cache_stats_breakdown[INST_ACC_R][HIT_RESERVED] = 0
Total_core_cache_stats_breakdown[INST_ACC_R][MISS] = 0
Total_core_cache_stats_breakdown[INST_ACC_R][RESERVATION_FAIL] = 0
Total_core_cache_stats_breakdown[INST_ACC_R][SECTOR_MISS] = 0
Total_core_cache_stats_breakdown[L1_WR_ALLOC_R][HIT] = 0
Total_core_cache_stats_breakdown[L1_WR_ALLOC_R][HIT_RESERVED] = 0
Total_core_cache_stats_breakdown[L1_WR_ALLOC_R][MISS] = 0
Total_core_cache_stats_breakdown[L1_WR_ALLOC_R][RESERVATION_FAIL] = 0
Total_core_cache_stats_breakdown[L1_WR_ALLOC_R][SECTOR_MISS] = 0
Total_core_cache_stats_breakdown[L2_WR_ALLOC_R][HIT] = 0
Total_core_cache_stats_breakdown[L2_WR_ALLOC_R][HIT_RESERVED] = 0
Total_core_cache_stats_breakdown[L2_WR_ALLOC_R][MISS] = 0
Total_core_cache_stats_breakdown[L2_WR_ALLOC_R][RESERVATION_FAIL] = 0
Total_core_cache_stats_breakdown[L2_WR_ALLOC_R][SECTOR_MISS] = 0
Total_core_cache_stats_breakdown[GLOBAL_ACC_R][TOTAL_ACCESS] = 13
Total_core_cache_stats_breakdown[GLOBAL_ACC_W][TOTAL_ACCESS] = 61
Total_core_cache_fail_stats:
ctas_completed 3, Shader 0 warp_id issue ditsribution:
warp_id:
0, 1,
distro:
36, 36,
gpgpu_n_tot_thrd_icount = 6080
gpgpu_n_tot_w_icount = 190
gpgpu_n_stall_shd_mem = 60
gpgpu_n_mem_read_local = 0
gpgpu_n_mem_write_local = 0
gpgpu_n_mem_read_global = 13
gpgpu_n_mem_write_global = 61
gpgpu_n_mem_texture = 0
gpgpu_n_mem_const = 0
gpgpu_n_load_insn = 97
gpgpu_n_store_insn = 289
gpgpu_n_shmem_insn = 0
gpgpu_n_sstarr_insn = 0
gpgpu_n_tex_insn = 0
gpgpu_n_const_mem_insn = 0
gpgpu_n_param_mem_insn = 960
gpgpu_n_shmem_bkconflict = 0
gpgpu_n_cache_bkconflict = 0
gpgpu_n_intrawarp_mshr_merge = 0
gpgpu_n_cmem_portconflict = 0
gpgpu_stall_shd_mem[c_mem][resource_stall] = 0
gpgpu_stall_shd_mem[s_mem][bk_conf] = 0
gpgpu_stall_shd_mem[gl_mem][resource_stall] = 60
gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0
gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0
gpu_reg_bank_conflict_stalls = 0
Warp Occupancy Distribution:
Stall:0 W0_Idle:3899 W0_Scoreboard:1255 W1:13 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:177
single_issue_nums: WS0:95 WS1:95 WS2:0 WS3:0
dual_issue_nums: WS0:0 WS1:0 WS2:0 WS3:0
traffic_breakdown_coretomem[GLOBAL_ACC_R] = 104 {8:13,}
traffic_breakdown_coretomem[GLOBAL_ACC_W] = 2440 {40:61,}
traffic_breakdown_memtocore[GLOBAL_ACC_R] = 520 {40:13,}
traffic_breakdown_memtocore[GLOBAL_ACC_W] = 488 {8:61,}
maxmflatency = 187
max_icnt2mem_latency = 23
maxmrqlatency = 0
max_icnt2sh_latency = 2
averagemflatency = 187
avg_icnt2mem_latency = 40
avg_icnt2sh_latency = 3
mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
mf_lat_table:0 0 0 0 0 0 0 74 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
icnt2mem_lat_table:0 0 0 0 74 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
icnt2sh_lat_table:0 74 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
mf_lat_pw_table:0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
maximum concurrent accesses to same row:
dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[11]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[12]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[13]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[14]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[15]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[16]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[17]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[18]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[19]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[20]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[21]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[22]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[23]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[24]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[25]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[26]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[27]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[28]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[29]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[30]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[31]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
maximum service time to same row:
dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[11]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[12]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[13]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[14]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[15]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[16]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[17]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[18]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[19]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[20]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[21]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[22]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[23]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[24]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[25]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[26]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[27]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[28]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[29]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[30]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[31]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
average row accesses per activate:
dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
dram[11]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
dram[12]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
dram[13]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
dram[14]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
dram[15]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
dram[16]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
dram[17]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
dram[18]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
dram[19]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
dram[20]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
dram[21]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
dram[22]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
dram[23]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
dram[24]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
dram[25]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
dram[26]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
dram[27]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
dram[28]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
dram[29]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
dram[30]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
dram[31]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
average row locality = 0/0 = -nan
number of total memory accesses made:
dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[11]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[12]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[13]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[14]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[15]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[16]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[17]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[18]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[19]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[20]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[21]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[22]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[23]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[24]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[25]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[26]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[27]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[28]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[29]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[30]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[31]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
total accesses: 0
min_bank_accesses = 0!
min_chip_accesses = 0!
number of total read accesses:
dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[11]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[12]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[13]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[14]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[15]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[16]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[17]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[18]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[19]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[20]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[21]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[22]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[23]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[24]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[25]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[26]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[27]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[28]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[29]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[30]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[31]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
total dram reads = 0
min_bank_accesses = 0!
min_chip_accesses = 0!
number of total write accesses:
dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[11]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[12]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[13]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[14]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[15]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[16]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[17]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[18]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[19]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[20]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[21]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[22]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[23]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[24]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[25]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[26]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[27]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[28]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[29]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[30]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[31]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
total dram writes = 0
min_bank_accesses = 0!
min_chip_accesses = 0!
average mf latency per bank:
dram[0]: none none none none none none none none none none none none none none none none
dram[1]: none none none none none none none none none none none none none none none none
dram[2]: none none none none none none none none none none none none none none none none
dram[3]: none none none none none none none none none none none none none none none none
dram[4]: none none none none none none none none none none none none none none none none
dram[5]: none none none none none none none none none none none none none none none none
dram[6]: none none none none none none none none none none none none none none none none
dram[7]: none none none none none none none none none none none none none none none none
dram[8]: none none none none none none none none none none none none none none none none
dram[9]: none none none none none none none none none none none none none none none none
dram[10]: none none none none none none none none none none none none none none none none
dram[11]: none none none none none none none none none none none none none none none none
dram[12]: none none none none none none none none none none none none none none none none
dram[13]: none none none none none none none none none none none none none none none none
dram[14]: none none none none none none none none none none none none none none none none
dram[15]: none none none none none none none none none none none none none none none none
dram[16]: none none none none none none none none none none none none none none none none
dram[17]: none none none none none none none none none none none none none none none none
dram[18]: none none none none none none none none none none none none none none none none
dram[19]: none none none none none none none none none none none none none none none none
dram[20]: none none none none none none none none none none none none none none none none
dram[21]: none none none none none none none none none none none none none none none none
dram[22]: none none none none none none none none none none none none none none none none
dram[23]: none none none none none none none none none none none none none none none none
dram[24]: none none none none none none none none none none none none none none none none
dram[25]: none none none none none none none none none none none none none none none none
dram[26]: none none none none none none none none none none none none none none none none
dram[27]: none none none none none none none none none none none none none none none none
dram[28]: none none none none none none none none none none none none none none none none
dram[29]: none none none none none none none none none none none none none none none none
dram[30]: none none none none none none none none none none none none none none none none
dram[31]: none none none none none none none none none none none none none none none none
maximum mf latency per bank:
dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[8]: 187 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[9]: 187 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[10]: 187 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[11]: 187 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[12]: 187 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[13]: 187 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[14]: 187 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[15]: 187 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[16]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[17]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[18]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[19]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[20]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[21]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[22]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[23]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[24]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[25]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[26]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[27]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[28]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[29]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[30]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[31]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Memory Partition 0:
Cache L2_bank_000:
MSHR contents
Cache L2_bank_001:
MSHR contents
In Dram Latency Queue (total = 0):
DRAM[0]: 16 bks, busW=16 BL=2 CL=12, tRRD=3 tCCD=1, tRCD=12 tRAS=28 tRP=12 tRC=40
n_cmd=4154 n_nop=4154 n_act=0 n_pre=0 n_ref_event=0 n_req=0 n_rd=0 n_rd_L2_A=0 n_write=0 n_wr_bk=0 bw_util=0
n_activity=0 dram_eff=-nan
bk0: 0a 4154i bk1: 0a 4154i bk2: 0a 4154i bk3: 0a 4154i bk4: 0a 4154i bk5: 0a 4154i bk6: 0a 4154i bk7: 0a 4154i bk8: 0a 4154i bk9: 0a 4154i bk10: 0a 4154i bk11: 0a 4154i bk12: 0a 4154i bk13: 0a 4154i bk14: 0a 4154i bk15: 0a 4154i
------------------------------------------------------------------------
Row_Buffer_Locality = -nan
Row_Buffer_Locality_read = -nan
Row_Buffer_Locality_write = -nan
Bank_Level_Parallism = -nan
Bank_Level_Parallism_Col = -nan
Bank_Level_Parallism_Ready = -nan
write_to_read_ratio_blp_rw_average = -nan
GrpLevelPara = -nan
BW Util details:
bwutil = 0.000000
total_CMD = 4154
util_bw = 0
Wasted_Col = 0
Wasted_Row = 0
Idle = 4154
BW Util Bottlenecks:
RCDc_limit = 0
RCDWRc_limit = 0
WTRc_limit = 0
RTWc_limit = 0
CCDLc_limit = 0
rwq = 0
CCDLc_limit_alone = 0
WTRc_limit_alone = 0
RTWc_limit_alone = 0
Commands details:
total_CMD = 4154
n_nop = 4154
Read = 0
Write = 0
L2_Alloc = 0
L2_WB = 0
n_act = 0
n_pre = 0
n_ref = 0
n_req = 0
total_req = 0
Dual Bus Interface Util:
issued_total_row = 0
issued_total_col = 0
Row_Bus_Util = 0.000000
CoL_Bus_Util = 0.000000
Either_Row_CoL_Bus_Util = 0.000000
Issued_on_Two_Bus_Simul_Util = 0.000000
issued_two_Eff = -nan
queue_avg = 0.000000
dram_util_bins: 0 0 0 0 0 0 0 0 0 0
dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
mrqq: max=0 avg=0
Memory Partition 1:
Cache L2_bank_002:
MSHR contents
Cache L2_bank_003:
MSHR contents
In Dram Latency Queue (total = 0):
DRAM[1]: 16 bks, busW=16 BL=2 CL=12, tRRD=3 tCCD=1, tRCD=12 tRAS=28 tRP=12 tRC=40
n_cmd=4154 n_nop=4154 n_act=0 n_pre=0 n_ref_event=0 n_req=0 n_rd=0 n_rd_L2_A=0 n_write=0 n_wr_bk=0 bw_util=0
n_activity=0 dram_eff=-nan
bk0: 0a 4154i bk1: 0a 4154i bk2: 0a 4154i bk3: 0a 4154i bk4: 0a 4154i bk5: 0a 4154i bk6: 0a 4154i bk7: 0a 4154i bk8: 0a 4154i bk9: 0a 4154i bk10: 0a 4154i bk11: 0a 4154i bk12: 0a 4154i bk13: 0a 4154i bk14: 0a 4154i bk15: 0a 4154i
------------------------------------------------------------------------
Row_Buffer_Locality = -nan
Row_Buffer_Locality_read = -nan
Row_Buffer_Locality_write = -nan
Bank_Level_Parallism = -nan
Bank_Level_Parallism_Col = -nan
Bank_Level_Parallism_Ready = -nan
write_to_read_ratio_blp_rw_average = -nan
GrpLevelPara = -nan
BW Util details:
bwutil = 0.000000
total_CMD = 4154
util_bw = 0
Wasted_Col = 0
Wasted_Row = 0
Idle = 4154
BW Util Bottlenecks:
RCDc_limit = 0
RCDWRc_limit = 0
WTRc_limit = 0
RTWc_limit = 0
CCDLc_limit = 0
rwq = 0
CCDLc_limit_alone = 0
WTRc_limit_alone = 0
RTWc_limit_alone = 0
Commands details:
total_CMD = 4154
n_nop = 4154
Read = 0
Write = 0
L2_Alloc = 0
L2_WB = 0
n_act = 0
n_pre = 0
n_ref = 0
n_req = 0
total_req = 0
Dual Bus Interface Util:
issued_total_row = 0
issued_total_col = 0
Row_Bus_Util = 0.000000
CoL_Bus_Util = 0.000000
Either_Row_CoL_Bus_Util = 0.000000
Issued_on_Two_Bus_Simul_Util = 0.000000
issued_two_Eff = -nan
queue_avg = 0.000000
dram_util_bins: 0 0 0 0 0 0 0 0 0 0
dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
mrqq: max=0 avg=0
Memory Partition 2:
Cache L2_bank_004:
MSHR contents
Cache L2_bank_005:
MSHR contents
In Dram Latency Queue (total = 0):
DRAM[2]: 16 bks, busW=16 BL=2 CL=12, tRRD=3 tCCD=1, tRCD=12 tRAS=28 tRP=12 tRC=40
n_cmd=4154 n_nop=4154 n_act=0 n_pre=0 n_ref_event=0 n_req=0 n_rd=0 n_rd_L2_A=0 n_write=0 n_wr_bk=0 bw_util=0
n_activity=0 dram_eff=-nan
bk0: 0a 4154i bk1: 0a 4154i bk2: 0a 4154i bk3: 0a 4154i bk4: 0a 4154i bk5: 0a 4154i bk6: 0a 4154i bk7: 0a 4154i bk8: 0a 4154i bk9: 0a 4154i bk10: 0a 4154i bk11: 0a 4154i bk12: 0a 4154i bk13: 0a 4154i bk14: 0a 4154i bk15: 0a 4154i
------------------------------------------------------------------------
Row_Buffer_Locality = -nan
Row_Buffer_Locality_read = -nan
Row_Buffer_Locality_write = -nan
Bank_Level_Parallism = -nan
Bank_Level_Parallism_Col = -nan
Bank_Level_Parallism_Ready = -nan
write_to_read_ratio_blp_rw_average = -nan
GrpLevelPara = -nan
BW Util details:
bwutil = 0.000000
total_CMD = 4154
util_bw = 0
Wasted_Col = 0
Wasted_Row = 0
Idle = 4154
BW Util Bottlenecks:
RCDc_limit = 0
RCDWRc_limit = 0
WTRc_limit = 0
RTWc_limit = 0
CCDLc_limit = 0
rwq = 0
CCDLc_limit_alone = 0
WTRc_limit_alone = 0
RTWc_limit_alone = 0
Commands details:
total_CMD = 4154
n_nop = 4154
Read = 0
Write = 0
L2_Alloc = 0
L2_WB = 0
n_act = 0
n_pre = 0
n_ref = 0
n_req = 0
total_req = 0
Dual Bus Interface Util:
issued_total_row = 0
issued_total_col = 0
Row_Bus_Util = 0.000000
CoL_Bus_Util = 0.000000
Either_Row_CoL_Bus_Util = 0.000000
Issued_on_Two_Bus_Simul_Util = 0.000000
issued_two_Eff = -nan
queue_avg = 0.000000
dram_util_bins: 0 0 0 0 0 0 0 0 0 0
dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
mrqq: max=0 avg=0
Memory Partition 3:
Cache L2_bank_006:
MSHR contents
Cache L2_bank_007:
MSHR contents
In Dram Latency Queue (total = 0):
DRAM[3]: 16 bks, busW=16 BL=2 CL=12, tRRD=3 tCCD=1, tRCD=12 tRAS=28 tRP=12 tRC=40
n_cmd=4154 n_nop=4154 n_act=0 n_pre=0 n_ref_event=0 n_req=0 n_rd=0 n_rd_L2_A=0 n_write=0 n_wr_bk=0 bw_util=0
n_activity=0 dram_eff=-nan
bk0: 0a 4154i bk1: 0a 4154i bk2: 0a 4154i bk3: 0a 4154i bk4: 0a 4154i bk5: 0a 4154i bk6: 0a 4154i bk7: 0a 4154i bk8: 0a 4154i bk9: 0a 4154i bk10: 0a 4154i bk11: 0a 4154i bk12: 0a 4154i bk13: 0a 4154i bk14: 0a 4154i bk15: 0a 4154i
------------------------------------------------------------------------
Row_Buffer_Locality = -nan
Row_Buffer_Locality_read = -nan
Row_Buffer_Locality_write = -nan
Bank_Level_Parallism = -nan
Bank_Level_Parallism_Col = -nan
Bank_Level_Parallism_Ready = -nan
write_to_read_ratio_blp_rw_average = -nan
GrpLevelPara = -nan
BW Util details:
bwutil = 0.000000
total_CMD = 4154
util_bw = 0
Wasted_Col = 0
Wasted_Row = 0
Idle = 4154
BW Util Bottlenecks:
RCDc_limit = 0
RCDWRc_limit = 0
WTRc_limit = 0
RTWc_limit = 0
CCDLc_limit = 0
rwq = 0
CCDLc_limit_alone = 0
WTRc_limit_alone = 0
RTWc_limit_alone = 0
Commands details:
total_CMD = 4154
n_nop = 4154
Read = 0
Write = 0
L2_Alloc = 0
L2_WB = 0
n_act = 0
n_pre = 0
n_ref = 0
n_req = 0
total_req = 0
Dual Bus Interface Util:
issued_total_row = 0
issued_total_col = 0
Row_Bus_Util = 0.000000
CoL_Bus_Util = 0.000000
Either_Row_CoL_Bus_Util = 0.000000
Issued_on_Two_Bus_Simul_Util = 0.000000
issued_two_Eff = -nan
queue_avg = 0.000000
dram_util_bins: 0 0 0 0 0 0 0 0 0 0
dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
mrqq: max=0 avg=0
Memory Partition 4:
Cache L2_bank_008:
MSHR contents
Cache L2_bank_009:
MSHR contents
In Dram Latency Queue (total = 0):
DRAM[4]: 16 bks, busW=16 BL=2 CL=12, tRRD=3 tCCD=1, tRCD=12 tRAS=28 tRP=12 tRC=40
n_cmd=4154 n_nop=4154 n_act=0 n_pre=0 n_ref_event=0 n_req=0 n_rd=0 n_rd_L2_A=0 n_write=0 n_wr_bk=0 bw_util=0
n_activity=0 dram_eff=-nan
bk0: 0a 4154i bk1: 0a 4154i bk2: 0a 4154i bk3: 0a 4154i bk4: 0a 4154i bk5: 0a 4154i bk6: 0a 4154i bk7: 0a 4154i bk8: 0a 4154i bk9: 0a 4154i bk10: 0a 4154i bk11: 0a 4154i bk12: 0a 4154i bk13: 0a 4154i bk14: 0a 4154i bk15: 0a 4154i
------------------------------------------------------------------------
Row_Buffer_Locality = -nan
Row_Buffer_Locality_read = -nan
Row_Buffer_Locality_write = -nan
Bank_Level_Parallism = -nan
Bank_Level_Parallism_Col = -nan
Bank_Level_Parallism_Ready = -nan
write_to_read_ratio_blp_rw_average = -nan
GrpLevelPara = -nan
BW Util details:
bwutil = 0.000000
total_CMD = 4154
util_bw = 0
Wasted_Col = 0
Wasted_Row = 0
Idle = 4154
BW Util Bottlenecks:
RCDc_limit = 0
RCDWRc_limit = 0
WTRc_limit = 0
RTWc_limit = 0
CCDLc_limit = 0
rwq = 0
CCDLc_limit_alone = 0
WTRc_limit_alone = 0
RTWc_limit_alone = 0
Commands details:
total_CMD = 4154
n_nop = 4154
Read = 0
Write = 0
L2_Alloc = 0
L2_WB = 0
n_act = 0
n_pre = 0
n_ref = 0
n_req = 0
total_req = 0
Dual Bus Interface Util:
issued_total_row = 0
issued_total_col = 0
Row_Bus_Util = 0.000000
CoL_Bus_Util = 0.000000
Either_Row_CoL_Bus_Util = 0.000000
Issued_on_Two_Bus_Simul_Util = 0.000000
issued_two_Eff = -nan
queue_avg = 0.000000
dram_util_bins: 0 0 0 0 0 0 0 0 0 0
dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
mrqq: max=0 avg=0
Memory Partition 5:
Cache L2_bank_010:
MSHR contents
Cache L2_bank_011:
MSHR contents
In Dram Latency Queue (total = 0):
DRAM[5]: 16 bks, busW=16 BL=2 CL=12, tRRD=3 tCCD=1, tRCD=12 tRAS=28 tRP=12 tRC=40
n_cmd=4154 n_nop=4154 n_act=0 n_pre=0 n_ref_event=0 n_req=0 n_rd=0 n_rd_L2_A=0 n_write=0 n_wr_bk=0 bw_util=0
n_activity=0 dram_eff=-nan
bk0: 0a 4154i bk1: 0a 4154i bk2: 0a 4154i bk3: 0a 4154i bk4: 0a 4154i bk5: 0a 4154i bk6: 0a 4154i bk7: 0a 4154i bk8: 0a 4154i bk9: 0a 4154i bk10: 0a 4154i bk11: 0a 4154i bk12: 0a 4154i bk13: 0a 4154i bk14: 0a 4154i bk15: 0a 4154i
------------------------------------------------------------------------
Row_Buffer_Locality = -nan
Row_Buffer_Locality_read = -nan
Row_Buffer_Locality_write = -nan
Bank_Level_Parallism = -nan
Bank_Level_Parallism_Col = -nan
Bank_Level_Parallism_Ready = -nan
write_to_read_ratio_blp_rw_average = -nan
GrpLevelPara = -nan
BW Util details:
bwutil = 0.000000
total_CMD = 4154
util_bw = 0
Wasted_Col = 0
Wasted_Row = 0
Idle = 4154
BW Util Bottlenecks:
RCDc_limit = 0
RCDWRc_limit = 0
WTRc_limit = 0
RTWc_limit = 0
CCDLc_limit = 0
rwq = 0
CCDLc_limit_alone = 0
WTRc_limit_alone = 0
RTWc_limit_alone = 0
Commands details:
total_CMD = 4154
n_nop = 4154
Read = 0
Write = 0
L2_Alloc = 0
L2_WB = 0
n_act = 0
n_pre = 0
n_ref = 0
n_req = 0
total_req = 0
Dual Bus Interface Util:
issued_total_row = 0
issued_total_col = 0
Row_Bus_Util = 0.000000
CoL_Bus_Util = 0.000000
Either_Row_CoL_Bus_Util = 0.000000
Issued_on_Two_Bus_Simul_Util = 0.000000
issued_two_Eff = -nan
queue_avg = 0.000000
dram_util_bins: 0 0 0 0 0 0 0 0 0 0
dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
mrqq: max=0 avg=0
Memory Partition 6:
Cache L2_bank_012:
MSHR contents
Cache L2_bank_013:
MSHR contents
In Dram Latency Queue (total = 0):
DRAM[6]: 16 bks, busW=16 BL=2 CL=12, tRRD=3 tCCD=1, tRCD=12 tRAS=28 tRP=12 tRC=40
n_cmd=4154 n_nop=4154 n_act=0 n_pre=0 n_ref_event=0 n_req=0 n_rd=0 n_rd_L2_A=0 n_write=0 n_wr_bk=0 bw_util=0
n_activity=0 dram_eff=-nan
bk0: 0a 4154i bk1: 0a 4154i bk2: 0a 4154i bk3: 0a 4154i bk4: 0a 4154i bk5: 0a 4154i bk6: 0a 4154i bk7: 0a 4154i bk8: 0a 4154i bk9: 0a 4154i bk10: 0a 4154i bk11: 0a 4154i bk12: 0a 4154i bk13: 0a 4154i bk14: 0a 4154i bk15: 0a 4154i
------------------------------------------------------------------------
Row_Buffer_Locality = -nan
Row_Buffer_Locality_read = -nan
Row_Buffer_Locality_write = -nan
Bank_Level_Parallism = -nan
Bank_Level_Parallism_Col = -nan
Bank_Level_Parallism_Ready = -nan
write_to_read_ratio_blp_rw_average = -nan
GrpLevelPara = -nan
BW Util details:
bwutil = 0.000000
total_CMD = 4154
util_bw = 0
Wasted_Col = 0
Wasted_Row = 0
Idle = 4154
BW Util Bottlenecks:
RCDc_limit = 0
RCDWRc_limit = 0
WTRc_limit = 0
RTWc_limit = 0
CCDLc_limit = 0
rwq = 0
CCDLc_limit_alone = 0
WTRc_limit_alone = 0
RTWc_limit_alone = 0
Commands details:
total_CMD = 4154
n_nop = 4154
Read = 0
Write = 0
L2_Alloc = 0
L2_WB = 0
n_act = 0
n_pre = 0
n_ref = 0
n_req = 0
total_req = 0
Dual Bus Interface Util:
issued_total_row = 0
issued_total_col = 0
Row_Bus_Util = 0.000000
CoL_Bus_Util = 0.000000
Either_Row_CoL_Bus_Util = 0.000000
Issued_on_Two_Bus_Simul_Util = 0.000000
issued_two_Eff = -nan
queue_avg = 0.000000
dram_util_bins: 0 0 0 0 0 0 0 0 0 0
dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
mrqq: max=0 avg=0
Memory Partition 7:
Cache L2_bank_014:
MSHR contents
Cache L2_bank_015:
MSHR contents
In Dram Latency Queue (total = 0):
DRAM[7]: 16 bks, busW=16 BL=2 CL=12, tRRD=3 tCCD=1, tRCD=12 tRAS=28 tRP=12 tRC=40
n_cmd=4154 n_nop=4154 n_act=0 n_pre=0 n_ref_event=0 n_req=0 n_rd=0 n_rd_L2_A=0 n_write=0 n_wr_bk=0 bw_util=0
n_activity=0 dram_eff=-nan
bk0: 0a 4154i bk1: 0a 4154i bk2: 0a 4154i bk3: 0a 4154i bk4: 0a 4154i bk5: 0a 4154i bk6: 0a 4154i bk7: 0a 4154i bk8: 0a 4154i bk9: 0a 4154i bk10: 0a 4154i bk11: 0a 4154i bk12: 0a 4154i bk13: 0a 4154i bk14: 0a 4154i bk15: 0a 4154i
------------------------------------------------------------------------
Row_Buffer_Locality = -nan
Row_Buffer_Locality_read = -nan
Row_Buffer_Locality_write = -nan
Bank_Level_Parallism = -nan
Bank_Level_Parallism_Col = -nan
Bank_Level_Parallism_Ready = -nan
write_to_read_ratio_blp_rw_average = -nan
GrpLevelPara = -nan
BW Util details:
bwutil = 0.000000
total_CMD = 4154
util_bw = 0
Wasted_Col = 0
Wasted_Row = 0
Idle = 4154
BW Util Bottlenecks:
RCDc_limit = 0
RCDWRc_limit = 0
WTRc_limit = 0
RTWc_limit = 0
CCDLc_limit = 0
rwq = 0
CCDLc_limit_alone = 0
WTRc_limit_alone = 0
RTWc_limit_alone = 0
Commands details:
total_CMD = 4154
n_nop = 4154
Read = 0
Write = 0
L2_Alloc = 0
L2_WB = 0
n_act = 0
n_pre = 0
n_ref = 0
n_req = 0
total_req = 0
Dual Bus Interface Util:
issued_total_row = 0
issued_total_col = 0
Row_Bus_Util = 0.000000
CoL_Bus_Util = 0.000000
Either_Row_CoL_Bus_Util = 0.000000
Issued_on_Two_Bus_Simul_Util = 0.000000
issued_two_Eff = -nan
queue_avg = 0.000000
dram_util_bins: 0 0 0 0 0 0 0 0 0 0
dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
mrqq: max=0 avg=0
Memory Partition 8:
Cache L2_bank_016:
MSHR contents
Cache L2_bank_017:
MSHR contents
In Dram Latency Queue (total = 0):
DRAM[8]: 16 bks, busW=16 BL=2 CL=12, tRRD=3 tCCD=1, tRCD=12 tRAS=28 tRP=12 tRC=40
n_cmd=4154 n_nop=4154 n_act=0 n_pre=0 n_ref_event=0 n_req=0 n_rd=0 n_rd_L2_A=0 n_write=0 n_wr_bk=0 bw_util=0
n_activity=0 dram_eff=-nan
bk0: 0a 4154i bk1: 0a 4154i bk2: 0a 4154i bk3: 0a 4154i bk4: 0a 4154i bk5: 0a 4154i bk6: 0a 4154i bk7: 0a 4154i bk8: 0a 4154i bk9: 0a 4154i bk10: 0a 4154i bk11: 0a 4154i bk12: 0a 4154i bk13: 0a 4154i bk14: 0a 4154i bk15: 0a 4154i
------------------------------------------------------------------------
Row_Buffer_Locality = -nan
Row_Buffer_Locality_read = -nan
Row_Buffer_Locality_write = -nan
Bank_Level_Parallism = -nan
Bank_Level_Parallism_Col = -nan
Bank_Level_Parallism_Ready = -nan
write_to_read_ratio_blp_rw_average = -nan
GrpLevelPara = -nan
BW Util details:
bwutil = 0.000000
total_CMD = 4154
util_bw = 0
Wasted_Col = 0
Wasted_Row = 0
Idle = 4154
BW Util Bottlenecks:
RCDc_limit = 0
RCDWRc_limit = 0
WTRc_limit = 0
RTWc_limit = 0
CCDLc_limit = 0
rwq = 0
CCDLc_limit_alone = 0
WTRc_limit_alone = 0
RTWc_limit_alone = 0
Commands details:
total_CMD = 4154
n_nop = 4154
Read = 0
Write = 0
L2_Alloc = 0
L2_WB = 0
n_act = 0
n_pre = 0
n_ref = 0
n_req = 0
total_req = 0
Dual Bus Interface Util:
issued_total_row = 0
issued_total_col = 0
Row_Bus_Util = 0.000000
CoL_Bus_Util = 0.000000
Either_Row_CoL_Bus_Util = 0.000000
Issued_on_Two_Bus_Simul_Util = 0.000000
issued_two_Eff = -nan
queue_avg = 0.000000
dram_util_bins: 0 0 0 0 0 0 0 0 0 0
dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
mrqq: max=0 avg=0
Memory Partition 9:
Cache L2_bank_018:
MSHR contents
Cache L2_bank_019:
MSHR contents
In Dram Latency Queue (total = 0):
DRAM[9]: 16 bks, busW=16 BL=2 CL=12, tRRD=3 tCCD=1, tRCD=12 tRAS=28 tRP=12 tRC=40
n_cmd=4154 n_nop=4154 n_act=0 n_pre=0 n_ref_event=0 n_req=0 n_rd=0 n_rd_L2_A=0 n_write=0 n_wr_bk=0 bw_util=0
n_activity=0 dram_eff=-nan
bk0: 0a 4154i bk1: 0a 4154i bk2: 0a 4154i bk3: 0a 4154i bk4: 0a 4154i bk5: 0a 4154i bk6: 0a 4154i bk7: 0a 4154i bk8: 0a 4154i bk9: 0a 4154i bk10: 0a 4154i bk11: 0a 4154i bk12: 0a 4154i bk13: 0a 4154i bk14: 0a 4154i bk15: 0a 4154i
------------------------------------------------------------------------
Row_Buffer_Locality = -nan
Row_Buffer_Locality_read = -nan
Row_Buffer_Locality_write = -nan
Bank_Level_Parallism = -nan
Bank_Level_Parallism_Col = -nan
Bank_Level_Parallism_Ready = -nan
write_to_read_ratio_blp_rw_average = -nan
GrpLevelPara = -nan
BW Util details:
bwutil = 0.000000
total_CMD = 4154
util_bw = 0
Wasted_Col = 0
Wasted_Row = 0
Idle = 4154
BW Util Bottlenecks:
RCDc_limit = 0
RCDWRc_limit = 0
WTRc_limit = 0
RTWc_limit = 0
CCDLc_limit = 0
rwq = 0
CCDLc_limit_alone = 0
WTRc_limit_alone = 0
RTWc_limit_alone = 0
Commands details:
total_CMD = 4154
n_nop = 4154
Read = 0
Write = 0
L2_Alloc = 0
L2_WB = 0
n_act = 0
n_pre = 0
n_ref = 0
n_req = 0
total_req = 0
Dual Bus Interface Util:
issued_total_row = 0
issued_total_col = 0
Row_Bus_Util = 0.000000
CoL_Bus_Util = 0.000000
Either_Row_CoL_Bus_Util = 0.000000
Issued_on_Two_Bus_Simul_Util = 0.000000
issued_two_Eff = -nan
queue_avg = 0.000000
dram_util_bins: 0 0 0 0 0 0 0 0 0 0
dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
mrqq: max=0 avg=0
Memory Partition 10:
Cache L2_bank_020:
MSHR contents
Cache L2_bank_021:
MSHR contents
In Dram Latency Queue (total = 0):
DRAM[10]: 16 bks, busW=16 BL=2 CL=12, tRRD=3 tCCD=1, tRCD=12 tRAS=28 tRP=12 tRC=40
n_cmd=4154 n_nop=4154 n_act=0 n_pre=0 n_ref_event=0 n_req=0 n_rd=0 n_rd_L2_A=0 n_write=0 n_wr_bk=0 bw_util=0
n_activity=0 dram_eff=-nan
bk0: 0a 4154i bk1: 0a 4154i bk2: 0a 4154i bk3: 0a 4154i bk4: 0a 4154i bk5: 0a 4154i bk6: 0a 4154i bk7: 0a 4154i bk8: 0a 4154i bk9: 0a 4154i bk10: 0a 4154i bk11: 0a 4154i bk12: 0a 4154i bk13: 0a 4154i bk14: 0a 4154i bk15: 0a 4154i
------------------------------------------------------------------------
Row_Buffer_Locality = -nan
Row_Buffer_Locality_read = -nan
Row_Buffer_Locality_write = -nan
Bank_Level_Parallism = -nan
Bank_Level_Parallism_Col = -nan
Bank_Level_Parallism_Ready = -nan
write_to_read_ratio_blp_rw_average = -nan
GrpLevelPara = -nan
BW Util details:
bwutil = 0.000000
total_CMD = 4154
util_bw = 0
Wasted_Col = 0
Wasted_Row = 0
Idle = 4154
BW Util Bottlenecks:
RCDc_limit = 0
RCDWRc_limit = 0
WTRc_limit = 0
RTWc_limit = 0
CCDLc_limit = 0
rwq = 0
CCDLc_limit_alone = 0
WTRc_limit_alone = 0
RTWc_limit_alone = 0
Commands details:
total_CMD = 4154
n_nop = 4154
Read = 0
Write = 0
L2_Alloc = 0
L2_WB = 0
n_act = 0
n_pre = 0
n_ref = 0
n_req = 0
total_req = 0
Dual Bus Interface Util:
issued_total_row = 0
issued_total_col = 0
Row_Bus_Util = 0.000000
CoL_Bus_Util = 0.000000
Either_Row_CoL_Bus_Util = 0.000000
Issued_on_Two_Bus_Simul_Util = 0.000000
issued_two_Eff = -nan
queue_avg = 0.000000
dram_util_bins: 0 0 0 0 0 0 0 0 0 0
dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
mrqq: max=0 avg=0
Memory Partition 11:
Cache L2_bank_022:
MSHR contents
Cache L2_bank_023:
MSHR contents
In Dram Latency Queue (total = 0):
DRAM[11]: 16 bks, busW=16 BL=2 CL=12, tRRD=3 tCCD=1, tRCD=12 tRAS=28 tRP=12 tRC=40
n_cmd=4154 n_nop=4154 n_act=0 n_pre=0 n_ref_event=0 n_req=0 n_rd=0 n_rd_L2_A=0 n_write=0 n_wr_bk=0 bw_util=0
n_activity=0 dram_eff=-nan
bk0: 0a 4154i bk1: 0a 4154i bk2: 0a 4154i bk3: 0a 4154i bk4: 0a 4154i bk5: 0a 4154i bk6: 0a 4154i bk7: 0a 4154i bk8: 0a 4154i bk9: 0a 4154i bk10: 0a 4154i bk11: 0a 4154i bk12: 0a 4154i bk13: 0a 4154i bk14: 0a 4154i bk15: 0a 4154i
------------------------------------------------------------------------
Row_Buffer_Locality = -nan
Row_Buffer_Locality_read = -nan
Row_Buffer_Locality_write = -nan
Bank_Level_Parallism = -nan
Bank_Level_Parallism_Col = -nan
Bank_Level_Parallism_Ready = -nan
write_to_read_ratio_blp_rw_average = -nan
GrpLevelPara = -nan
BW Util details:
bwutil = 0.000000
total_CMD = 4154
util_bw = 0
Wasted_Col = 0
Wasted_Row = 0
Idle = 4154
BW Util Bottlenecks:
RCDc_limit = 0
RCDWRc_limit = 0
WTRc_limit = 0
RTWc_limit = 0
CCDLc_limit = 0
rwq = 0
CCDLc_limit_alone = 0
WTRc_limit_alone = 0
RTWc_limit_alone = 0
Commands details:
total_CMD = 4154
n_nop = 4154
Read = 0
Write = 0
L2_Alloc = 0
L2_WB = 0
n_act = 0
n_pre = 0
n_ref = 0
n_req = 0
total_req = 0
Dual Bus Interface Util:
issued_total_row = 0
issued_total_col = 0
Row_Bus_Util = 0.000000
CoL_Bus_Util = 0.000000
Either_Row_CoL_Bus_Util = 0.000000
Issued_on_Two_Bus_Simul_Util = 0.000000
issued_two_Eff = -nan
queue_avg = 0.000000
dram_util_bins: 0 0 0 0 0 0 0 0 0 0
dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
mrqq: max=0 avg=0
Memory Partition 12:
Cache L2_bank_024:
MSHR contents
Cache L2_bank_025:
MSHR contents
In Dram Latency Queue (total = 0):
DRAM[12]: 16 bks, busW=16 BL=2 CL=12, tRRD=3 tCCD=1, tRCD=12 tRAS=28 tRP=12 tRC=40
n_cmd=4154 n_nop=4154 n_act=0 n_pre=0 n_ref_event=0 n_req=0 n_rd=0 n_rd_L2_A=0 n_write=0 n_wr_bk=0 bw_util=0
n_activity=0 dram_eff=-nan
bk0: 0a 4154i bk1: 0a 4154i bk2: 0a 4154i bk3: 0a 4154i bk4: 0a 4154i bk5: 0a 4154i bk6: 0a 4154i bk7: 0a 4154i bk8: 0a 4154i bk9: 0a 4154i bk10: 0a 4154i bk11: 0a 4154i bk12: 0a 4154i bk13: 0a 4154i bk14: 0a 4154i bk15: 0a 4154i
------------------------------------------------------------------------
Row_Buffer_Locality = -nan
Row_Buffer_Locality_read = -nan
Row_Buffer_Locality_write = -nan
Bank_Level_Parallism = -nan
Bank_Level_Parallism_Col = -nan
Bank_Level_Parallism_Ready = -nan
write_to_read_ratio_blp_rw_average = -nan
GrpLevelPara = -nan
BW Util details:
bwutil = 0.000000
total_CMD = 4154
util_bw = 0
Wasted_Col = 0
Wasted_Row = 0
Idle = 4154
BW Util Bottlenecks:
RCDc_limit = 0
RCDWRc_limit = 0
WTRc_limit = 0
RTWc_limit = 0
CCDLc_limit = 0
rwq = 0
CCDLc_limit_alone = 0
WTRc_limit_alone = 0
RTWc_limit_alone = 0
Commands details:
total_CMD = 4154
n_nop = 4154
Read = 0
Write = 0
L2_Alloc = 0
L2_WB = 0
n_act = 0
n_pre = 0
n_ref = 0
n_req = 0
total_req = 0
Dual Bus Interface Util:
issued_total_row = 0
issued_total_col = 0
Row_Bus_Util = 0.000000
CoL_Bus_Util = 0.000000
Either_Row_CoL_Bus_Util = 0.000000
Issued_on_Two_Bus_Simul_Util = 0.000000
issued_two_Eff = -nan
queue_avg = 0.000000
dram_util_bins: 0 0 0 0 0 0 0 0 0 0
dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
mrqq: max=0 avg=0
Memory Partition 13:
Cache L2_bank_026:
MSHR contents
Cache L2_bank_027:
MSHR contents
In Dram Latency Queue (total = 0):
DRAM[13]: 16 bks, busW=16 BL=2 CL=12, tRRD=3 tCCD=1, tRCD=12 tRAS=28 tRP=12 tRC=40
n_cmd=4154 n_nop=4154 n_act=0 n_pre=0 n_ref_event=0 n_req=0 n_rd=0 n_rd_L2_A=0 n_write=0 n_wr_bk=0 bw_util=0
n_activity=0 dram_eff=-nan
bk0: 0a 4154i bk1: 0a 4154i bk2: 0a 4154i bk3: 0a 4154i bk4: 0a 4154i bk5: 0a 4154i bk6: 0a 4154i bk7: 0a 4154i bk8: 0a 4154i bk9: 0a 4154i bk10: 0a 4154i bk11: 0a 4154i bk12: 0a 4154i bk13: 0a 4154i bk14: 0a 4154i bk15: 0a 4154i
------------------------------------------------------------------------
Row_Buffer_Locality = -nan
Row_Buffer_Locality_read = -nan
Row_Buffer_Locality_write = -nan
Bank_Level_Parallism = -nan
Bank_Level_Parallism_Col = -nan
Bank_Level_Parallism_Ready = -nan
write_to_read_ratio_blp_rw_average = -nan
GrpLevelPara = -nan
BW Util details:
bwutil = 0.000000
total_CMD = 4154
util_bw = 0
Wasted_Col = 0
Wasted_Row = 0
Idle = 4154
BW Util Bottlenecks:
RCDc_limit = 0
RCDWRc_limit = 0
WTRc_limit = 0
RTWc_limit = 0
CCDLc_limit = 0
rwq = 0
CCDLc_limit_alone = 0
WTRc_limit_alone = 0
RTWc_limit_alone = 0
Commands details:
total_CMD = 4154
n_nop = 4154
Read = 0
Write = 0
L2_Alloc = 0
L2_WB = 0
n_act = 0
n_pre = 0
n_ref = 0
n_req = 0
total_req = 0
Dual Bus Interface Util:
issued_total_row = 0
issued_total_col = 0
Row_Bus_Util = 0.000000
CoL_Bus_Util = 0.000000
Either_Row_CoL_Bus_Util = 0.000000
Issued_on_Two_Bus_Simul_Util = 0.000000
issued_two_Eff = -nan
queue_avg = 0.000000
dram_util_bins: 0 0 0 0 0 0 0 0 0 0
dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
mrqq: max=0 avg=0
Memory Partition 14:
Cache L2_bank_028:
MSHR contents
Cache L2_bank_029:
MSHR contents
In Dram Latency Queue (total = 0):
DRAM[14]: 16 bks, busW=16 BL=2 CL=12, tRRD=3 tCCD=1, tRCD=12 tRAS=28 tRP=12 tRC=40
n_cmd=4154 n_nop=4154 n_act=0 n_pre=0 n_ref_event=0 n_req=0 n_rd=0 n_rd_L2_A=0 n_write=0 n_wr_bk=0 bw_util=0
n_activity=0 dram_eff=-nan
bk0: 0a 4154i bk1: 0a 4154i bk2: 0a 4154i bk3: 0a 4154i bk4: 0a 4154i bk5: 0a 4154i bk6: 0a 4154i bk7: 0a 4154i bk8: 0a 4154i bk9: 0a 4154i bk10: 0a 4154i bk11: 0a 4154i bk12: 0a 4154i bk13: 0a 4154i bk14: 0a 4154i bk15: 0a 4154i
------------------------------------------------------------------------
Row_Buffer_Locality = -nan
Row_Buffer_Locality_read = -nan
Row_Buffer_Locality_write = -nan
Bank_Level_Parallism = -nan
Bank_Level_Parallism_Col = -nan
Bank_Level_Parallism_Ready = -nan
write_to_read_ratio_blp_rw_average = -nan
GrpLevelPara = -nan
BW Util details:
bwutil = 0.000000
total_CMD = 4154
util_bw = 0
Wasted_Col = 0
Wasted_Row = 0
Idle = 4154
BW Util Bottlenecks:
RCDc_limit = 0
RCDWRc_limit = 0
WTRc_limit = 0
RTWc_limit = 0
CCDLc_limit = 0
rwq = 0
CCDLc_limit_alone = 0
WTRc_limit_alone = 0
RTWc_limit_alone = 0
Commands details:
total_CMD = 4154
n_nop = 4154
Read = 0
Write = 0
L2_Alloc = 0
L2_WB = 0
n_act = 0
n_pre = 0
n_ref = 0
n_req = 0
total_req = 0
Dual Bus Interface Util:
issued_total_row = 0
issued_total_col = 0
Row_Bus_Util = 0.000000
CoL_Bus_Util = 0.000000
Either_Row_CoL_Bus_Util = 0.000000
Issued_on_Two_Bus_Simul_Util = 0.000000
issued_two_Eff = -nan
queue_avg = 0.000000
dram_util_bins: 0 0 0 0 0 0 0 0 0 0
dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
mrqq: max=0 avg=0
Memory Partition 15:
Cache L2_bank_030:
MSHR contents
Cache L2_bank_031:
MSHR contents
In Dram Latency Queue (total = 0):
DRAM[15]: 16 bks, busW=16 BL=2 CL=12, tRRD=3 tCCD=1, tRCD=12 tRAS=28 tRP=12 tRC=40
n_cmd=4154 n_nop=4154 n_act=0 n_pre=0 n_ref_event=0 n_req=0 n_rd=0 n_rd_L2_A=0 n_write=0 n_wr_bk=0 bw_util=0
n_activity=0 dram_eff=-nan
bk0: 0a 4154i bk1: 0a 4154i bk2: 0a 4154i bk3: 0a 4154i bk4: 0a 4154i bk5: 0a 4154i bk6: 0a 4154i bk7: 0a 4154i bk8: 0a 4154i bk9: 0a 4154i bk10: 0a 4154i bk11: 0a 4154i bk12: 0a 4154i bk13: 0a 4154i bk14: 0a 4154i bk15: 0a 4154i
------------------------------------------------------------------------
Row_Buffer_Locality = -nan
Row_Buffer_Locality_read = -nan
Row_Buffer_Locality_write = -nan
Bank_Level_Parallism = -nan
Bank_Level_Parallism_Col = -nan
Bank_Level_Parallism_Ready = -nan
write_to_read_ratio_blp_rw_average = -nan
GrpLevelPara = -nan
BW Util details:
bwutil = 0.000000
total_CMD = 4154
util_bw = 0
Wasted_Col = 0
Wasted_Row = 0
Idle = 4154
BW Util Bottlenecks:
RCDc_limit = 0
RCDWRc_limit = 0
WTRc_limit = 0
RTWc_limit = 0
CCDLc_limit = 0
rwq = 0
CCDLc_limit_alone = 0
WTRc_limit_alone = 0
RTWc_limit_alone = 0
Commands details:
total_CMD = 4154
n_nop = 4154
Read = 0
Write = 0
L2_Alloc = 0
L2_WB = 0
n_act = 0
n_pre = 0
n_ref = 0
n_req = 0
total_req = 0
Dual Bus Interface Util:
issued_total_row = 0
issued_total_col = 0
Row_Bus_Util = 0.000000
CoL_Bus_Util = 0.000000
Either_Row_CoL_Bus_Util = 0.000000
Issued_on_Two_Bus_Simul_Util = 0.000000
issued_two_Eff = -nan
queue_avg = 0.000000
dram_util_bins: 0 0 0 0 0 0 0 0 0 0
dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
mrqq: max=0 avg=0
Memory Partition 16:
Cache L2_bank_032:
MSHR contents
Cache L2_bank_033:
MSHR contents
In Dram Latency Queue (total = 0):
DRAM[16]: 16 bks, busW=16 BL=2 CL=12, tRRD=3 tCCD=1, tRCD=12 tRAS=28 tRP=12 tRC=40
n_cmd=4154 n_nop=4154 n_act=0 n_pre=0 n_ref_event=0 n_req=0 n_rd=0 n_rd_L2_A=0 n_write=0 n_wr_bk=0 bw_util=0
n_activity=0 dram_eff=-nan
bk0: 0a 4154i bk1: 0a 4154i bk2: 0a 4154i bk3: 0a 4154i bk4: 0a 4154i bk5: 0a 4154i bk6: 0a 4154i bk7: 0a 4154i bk8: 0a 4154i bk9: 0a 4154i bk10: 0a 4154i bk11: 0a 4154i bk12: 0a 4154i bk13: 0a 4154i bk14: 0a 4154i bk15: 0a 4154i
------------------------------------------------------------------------
Row_Buffer_Locality = -nan
Row_Buffer_Locality_read = -nan
Row_Buffer_Locality_write = -nan
Bank_Level_Parallism = -nan
Bank_Level_Parallism_Col = -nan
Bank_Level_Parallism_Ready = -nan
write_to_read_ratio_blp_rw_average = -nan
GrpLevelPara = -nan
BW Util details:
bwutil = 0.000000
total_CMD = 4154
util_bw = 0
Wasted_Col = 0
Wasted_Row = 0
Idle = 4154
BW Util Bottlenecks:
RCDc_limit = 0
RCDWRc_limit = 0
WTRc_limit = 0
RTWc_limit = 0
CCDLc_limit = 0
rwq = 0
CCDLc_limit_alone = 0
WTRc_limit_alone = 0
RTWc_limit_alone = 0
Commands details:
total_CMD = 4154
n_nop = 4154
Read = 0
Write = 0
L2_Alloc = 0
L2_WB = 0
n_act = 0
n_pre = 0
n_ref = 0
n_req = 0
total_req = 0
Dual Bus Interface Util:
issued_total_row = 0
issued_total_col = 0
Row_Bus_Util = 0.000000
CoL_Bus_Util = 0.000000
Either_Row_CoL_Bus_Util = 0.000000
Issued_on_Two_Bus_Simul_Util = 0.000000
issued_two_Eff = -nan
queue_avg = 0.000000
dram_util_bins: 0 0 0 0 0 0 0 0 0 0
dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
mrqq: max=0 avg=0
Memory Partition 17:
Cache L2_bank_034:
MSHR contents
Cache L2_bank_035:
MSHR contents
In Dram Latency Queue (total = 0):
DRAM[17]: 16 bks, busW=16 BL=2 CL=12, tRRD=3 tCCD=1, tRCD=12 tRAS=28 tRP=12 tRC=40
n_cmd=4154 n_nop=4154 n_act=0 n_pre=0 n_ref_event=0 n_req=0 n_rd=0 n_rd_L2_A=0 n_write=0 n_wr_bk=0 bw_util=0
n_activity=0 dram_eff=-nan
bk0: 0a 4154i bk1: 0a 4154i bk2: 0a 4154i bk3: 0a 4154i bk4: 0a 4154i bk5: 0a 4154i bk6: 0a 4154i bk7: 0a 4154i bk8: 0a 4154i bk9: 0a 4154i bk10: 0a 4154i bk11: 0a 4154i bk12: 0a 4154i bk13: 0a 4154i bk14: 0a 4154i bk15: 0a 4154i
------------------------------------------------------------------------
Row_Buffer_Locality = -nan
Row_Buffer_Locality_read = -nan
Row_Buffer_Locality_write = -nan
Bank_Level_Parallism = -nan
Bank_Level_Parallism_Col = -nan
Bank_Level_Parallism_Ready = -nan
write_to_read_ratio_blp_rw_average = -nan
GrpLevelPara = -nan
BW Util details:
bwutil = 0.000000
total_CMD = 4154
util_bw = 0
Wasted_Col = 0
Wasted_Row = 0
Idle = 4154
BW Util Bottlenecks:
RCDc_limit = 0
RCDWRc_limit = 0
WTRc_limit = 0
RTWc_limit = 0
CCDLc_limit = 0
rwq = 0
CCDLc_limit_alone = 0
WTRc_limit_alone = 0
RTWc_limit_alone = 0
Commands details:
total_CMD = 4154
n_nop = 4154
Read = 0
Write = 0
L2_Alloc = 0
L2_WB = 0
n_act = 0
n_pre = 0
n_ref = 0
n_req = 0
total_req = 0
Dual Bus Interface Util:
issued_total_row = 0
issued_total_col = 0
Row_Bus_Util = 0.000000
CoL_Bus_Util = 0.000000
Either_Row_CoL_Bus_Util = 0.000000
Issued_on_Two_Bus_Simul_Util = 0.000000
issued_two_Eff = -nan
queue_avg = 0.000000
dram_util_bins: 0 0 0 0 0 0 0 0 0 0
dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
mrqq: max=0 avg=0
Memory Partition 18:
Cache L2_bank_036:
MSHR contents
Cache L2_bank_037:
MSHR contents
In Dram Latency Queue (total = 0):
DRAM[18]: 16 bks, busW=16 BL=2 CL=12, tRRD=3 tCCD=1, tRCD=12 tRAS=28 tRP=12 tRC=40
n_cmd=4154 n_nop=4154 n_act=0 n_pre=0 n_ref_event=0 n_req=0 n_rd=0 n_rd_L2_A=0 n_write=0 n_wr_bk=0 bw_util=0
n_activity=0 dram_eff=-nan
bk0: 0a 4154i bk1: 0a 4154i bk2: 0a 4154i bk3: 0a 4154i bk4: 0a 4154i bk5: 0a 4154i bk6: 0a 4154i bk7: 0a 4154i bk8: 0a 4154i bk9: 0a 4154i bk10: 0a 4154i bk11: 0a 4154i bk12: 0a 4154i bk13: 0a 4154i bk14: 0a 4154i bk15: 0a 4154i
------------------------------------------------------------------------
Row_Buffer_Locality = -nan
Row_Buffer_Locality_read = -nan
Row_Buffer_Locality_write = -nan
Bank_Level_Parallism = -nan
Bank_Level_Parallism_Col = -nan
Bank_Level_Parallism_Ready = -nan
write_to_read_ratio_blp_rw_average = -nan
GrpLevelPara = -nan
BW Util details:
bwutil = 0.000000
total_CMD = 4154
util_bw = 0
Wasted_Col = 0
Wasted_Row = 0
Idle = 4154
BW Util Bottlenecks:
RCDc_limit = 0
RCDWRc_limit = 0
WTRc_limit = 0
RTWc_limit = 0
CCDLc_limit = 0
rwq = 0
CCDLc_limit_alone = 0
WTRc_limit_alone = 0
RTWc_limit_alone = 0
Commands details:
total_CMD = 4154
n_nop = 4154
Read = 0
Write = 0
L2_Alloc = 0
L2_WB = 0
n_act = 0
n_pre = 0
n_ref = 0
n_req = 0
total_req = 0
Dual Bus Interface Util:
issued_total_row = 0
issued_total_col = 0
Row_Bus_Util = 0.000000
CoL_Bus_Util = 0.000000
Either_Row_CoL_Bus_Util = 0.000000
Issued_on_Two_Bus_Simul_Util = 0.000000
issued_two_Eff = -nan
queue_avg = 0.000000
dram_util_bins: 0 0 0 0 0 0 0 0 0 0
dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
mrqq: max=0 avg=0
Memory Partition 19:
Cache L2_bank_038:
MSHR contents
Cache L2_bank_039:
MSHR contents
In Dram Latency Queue (total = 0):
DRAM[19]: 16 bks, busW=16 BL=2 CL=12, tRRD=3 tCCD=1, tRCD=12 tRAS=28 tRP=12 tRC=40
n_cmd=4154 n_nop=4154 n_act=0 n_pre=0 n_ref_event=0 n_req=0 n_rd=0 n_rd_L2_A=0 n_write=0 n_wr_bk=0 bw_util=0
n_activity=0 dram_eff=-nan
bk0: 0a 4154i bk1: 0a 4154i bk2: 0a 4154i bk3: 0a 4154i bk4: 0a 4154i bk5: 0a 4154i bk6: 0a 4154i bk7: 0a 4154i bk8: 0a 4154i bk9: 0a 4154i bk10: 0a 4154i bk11: 0a 4154i bk12: 0a 4154i bk13: 0a 4154i bk14: 0a 4154i bk15: 0a 4154i
------------------------------------------------------------------------
Row_Buffer_Locality = -nan
Row_Buffer_Locality_read = -nan
Row_Buffer_Locality_write = -nan
Bank_Level_Parallism = -nan
Bank_Level_Parallism_Col = -nan
Bank_Level_Parallism_Ready = -nan
write_to_read_ratio_blp_rw_average = -nan
GrpLevelPara = -nan
BW Util details:
bwutil = 0.000000
total_CMD = 4154
util_bw = 0
Wasted_Col = 0
Wasted_Row = 0
Idle = 4154
BW Util Bottlenecks:
RCDc_limit = 0
RCDWRc_limit = 0
WTRc_limit = 0
RTWc_limit = 0
CCDLc_limit = 0
rwq = 0
CCDLc_limit_alone = 0
WTRc_limit_alone = 0
RTWc_limit_alone = 0
Commands details:
total_CMD = 4154
n_nop = 4154
Read = 0
Write = 0
L2_Alloc = 0
L2_WB = 0
n_act = 0
n_pre = 0
n_ref = 0
n_req = 0
total_req = 0
Dual Bus Interface Util:
issued_total_row = 0
issued_total_col = 0
Row_Bus_Util = 0.000000
CoL_Bus_Util = 0.000000
Either_Row_CoL_Bus_Util = 0.000000
Issued_on_Two_Bus_Simul_Util = 0.000000
issued_two_Eff = -nan
queue_avg = 0.000000
dram_util_bins: 0 0 0 0 0 0 0 0 0 0
dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
mrqq: max=0 avg=0
Memory Partition 20:
Cache L2_bank_040:
MSHR contents
Cache L2_bank_041:
MSHR contents
In Dram Latency Queue (total = 0):
DRAM[20]: 16 bks, busW=16 BL=2 CL=12, tRRD=3 tCCD=1, tRCD=12 tRAS=28 tRP=12 tRC=40
n_cmd=4154 n_nop=4154 n_act=0 n_pre=0 n_ref_event=0 n_req=0 n_rd=0 n_rd_L2_A=0 n_write=0 n_wr_bk=0 bw_util=0
n_activity=0 dram_eff=-nan
bk0: 0a 4154i bk1: 0a 4154i bk2: 0a 4154i bk3: 0a 4154i bk4: 0a 4154i bk5: 0a 4154i bk6: 0a 4154i bk7: 0a 4154i bk8: 0a 4154i bk9: 0a 4154i bk10: 0a 4154i bk11: 0a 4154i bk12: 0a 4154i bk13: 0a 4154i bk14: 0a 4154i bk15: 0a 4154i
------------------------------------------------------------------------
Row_Buffer_Locality = -nan
Row_Buffer_Locality_read = -nan
Row_Buffer_Locality_write = -nan
Bank_Level_Parallism = -nan
Bank_Level_Parallism_Col = -nan
Bank_Level_Parallism_Ready = -nan
write_to_read_ratio_blp_rw_average = -nan
GrpLevelPara = -nan
BW Util details:
bwutil = 0.000000
total_CMD = 4154
util_bw = 0
Wasted_Col = 0
Wasted_Row = 0
Idle = 4154
BW Util Bottlenecks:
RCDc_limit = 0
RCDWRc_limit = 0
WTRc_limit = 0
RTWc_limit = 0
CCDLc_limit = 0
rwq = 0
CCDLc_limit_alone = 0
WTRc_limit_alone = 0
RTWc_limit_alone = 0
Commands details:
total_CMD = 4154
n_nop = 4154
Read = 0
Write = 0
L2_Alloc = 0
L2_WB = 0
n_act = 0
n_pre = 0
n_ref = 0
n_req = 0
total_req = 0
Dual Bus Interface Util:
issued_total_row = 0
issued_total_col = 0
Row_Bus_Util = 0.000000
CoL_Bus_Util = 0.000000
Either_Row_CoL_Bus_Util = 0.000000
Issued_on_Two_Bus_Simul_Util = 0.000000
issued_two_Eff = -nan
queue_avg = 0.000000
dram_util_bins: 0 0 0 0 0 0 0 0 0 0
dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
mrqq: max=0 avg=0
Memory Partition 21:
Cache L2_bank_042:
MSHR contents
Cache L2_bank_043:
MSHR contents
In Dram Latency Queue (total = 0):
DRAM[21]: 16 bks, busW=16 BL=2 CL=12, tRRD=3 tCCD=1, tRCD=12 tRAS=28 tRP=12 tRC=40
n_cmd=4154 n_nop=4154 n_act=0 n_pre=0 n_ref_event=0 n_req=0 n_rd=0 n_rd_L2_A=0 n_write=0 n_wr_bk=0 bw_util=0
n_activity=0 dram_eff=-nan
bk0: 0a 4154i bk1: 0a 4154i bk2: 0a 4154i bk3: 0a 4154i bk4: 0a 4154i bk5: 0a 4154i bk6: 0a 4154i bk7: 0a 4154i bk8: 0a 4154i bk9: 0a 4154i bk10: 0a 4154i bk11: 0a 4154i bk12: 0a 4154i bk13: 0a 4154i bk14: 0a 4154i bk15: 0a 4154i
------------------------------------------------------------------------
Row_Buffer_Locality = -nan
Row_Buffer_Locality_read = -nan
Row_Buffer_Locality_write = -nan
Bank_Level_Parallism = -nan
Bank_Level_Parallism_Col = -nan
Bank_Level_Parallism_Ready = -nan
write_to_read_ratio_blp_rw_average = -nan
GrpLevelPara = -nan
BW Util details:
bwutil = 0.000000
total_CMD = 4154
util_bw = 0
Wasted_Col = 0
Wasted_Row = 0
Idle = 4154
BW Util Bottlenecks:
RCDc_limit = 0
RCDWRc_limit = 0
WTRc_limit = 0
RTWc_limit = 0
CCDLc_limit = 0
rwq = 0
CCDLc_limit_alone = 0
WTRc_limit_alone = 0
RTWc_limit_alone = 0
Commands details:
total_CMD = 4154
n_nop = 4154
Read = 0
Write = 0
L2_Alloc = 0
L2_WB = 0
n_act = 0
n_pre = 0
n_ref = 0
n_req = 0
total_req = 0
Dual Bus Interface Util:
issued_total_row = 0
issued_total_col = 0
Row_Bus_Util = 0.000000
CoL_Bus_Util = 0.000000
Either_Row_CoL_Bus_Util = 0.000000
Issued_on_Two_Bus_Simul_Util = 0.000000
issued_two_Eff = -nan
queue_avg = 0.000000
dram_util_bins: 0 0 0 0 0 0 0 0 0 0
dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
mrqq: max=0 avg=0
Memory Partition 22:
Cache L2_bank_044:
MSHR contents
Cache L2_bank_045:
MSHR contents
In Dram Latency Queue (total = 0):
DRAM[22]: 16 bks, busW=16 BL=2 CL=12, tRRD=3 tCCD=1, tRCD=12 tRAS=28 tRP=12 tRC=40
n_cmd=4154 n_nop=4154 n_act=0 n_pre=0 n_ref_event=0 n_req=0 n_rd=0 n_rd_L2_A=0 n_write=0 n_wr_bk=0 bw_util=0
n_activity=0 dram_eff=-nan
bk0: 0a 4154i bk1: 0a 4154i bk2: 0a 4154i bk3: 0a 4154i bk4: 0a 4154i bk5: 0a 4154i bk6: 0a 4154i bk7: 0a 4154i bk8: 0a 4154i bk9: 0a 4154i bk10: 0a 4154i bk11: 0a 4154i bk12: 0a 4154i bk13: 0a 4154i bk14: 0a 4154i bk15: 0a 4154i
------------------------------------------------------------------------
Row_Buffer_Locality = -nan
Row_Buffer_Locality_read = -nan
Row_Buffer_Locality_write = -nan
Bank_Level_Parallism = -nan
Bank_Level_Parallism_Col = -nan
Bank_Level_Parallism_Ready = -nan
write_to_read_ratio_blp_rw_average = -nan
GrpLevelPara = -nan
BW Util details:
bwutil = 0.000000
total_CMD = 4154
util_bw = 0
Wasted_Col = 0
Wasted_Row = 0
Idle = 4154
BW Util Bottlenecks:
RCDc_limit = 0
RCDWRc_limit = 0
WTRc_limit = 0
RTWc_limit = 0
CCDLc_limit = 0
rwq = 0
CCDLc_limit_alone = 0
WTRc_limit_alone = 0
RTWc_limit_alone = 0
Commands details:
total_CMD = 4154
n_nop = 4154
Read = 0
Write = 0
L2_Alloc = 0
L2_WB = 0
n_act = 0
n_pre = 0
n_ref = 0
n_req = 0
total_req = 0
Dual Bus Interface Util:
issued_total_row = 0
issued_total_col = 0
Row_Bus_Util = 0.000000
CoL_Bus_Util = 0.000000
Either_Row_CoL_Bus_Util = 0.000000
Issued_on_Two_Bus_Simul_Util = 0.000000
issued_two_Eff = -nan
queue_avg = 0.000000
dram_util_bins: 0 0 0 0 0 0 0 0 0 0
dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
mrqq: max=0 avg=0
Memory Partition 23:
Cache L2_bank_046:
MSHR contents
Cache L2_bank_047:
MSHR contents
In Dram Latency Queue (total = 0):
DRAM[23]: 16 bks, busW=16 BL=2 CL=12, tRRD=3 tCCD=1, tRCD=12 tRAS=28 tRP=12 tRC=40
n_cmd=4154 n_nop=4154 n_act=0 n_pre=0 n_ref_event=0 n_req=0 n_rd=0 n_rd_L2_A=0 n_write=0 n_wr_bk=0 bw_util=0
n_activity=0 dram_eff=-nan
bk0: 0a 4154i bk1: 0a 4154i bk2: 0a 4154i bk3: 0a 4154i bk4: 0a 4154i bk5: 0a 4154i bk6: 0a 4154i bk7: 0a 4154i bk8: 0a 4154i bk9: 0a 4154i bk10: 0a 4154i bk11: 0a 4154i bk12: 0a 4154i bk13: 0a 4154i bk14: 0a 4154i bk15: 0a 4154i
------------------------------------------------------------------------
Row_Buffer_Locality = -nan
Row_Buffer_Locality_read = -nan
Row_Buffer_Locality_write = -nan
Bank_Level_Parallism = -nan
Bank_Level_Parallism_Col = -nan
Bank_Level_Parallism_Ready = -nan
write_to_read_ratio_blp_rw_average = -nan
GrpLevelPara = -nan
BW Util details:
bwutil = 0.000000
total_CMD = 4154
util_bw = 0
Wasted_Col = 0
Wasted_Row = 0
Idle = 4154
BW Util Bottlenecks:
RCDc_limit = 0
RCDWRc_limit = 0
WTRc_limit = 0
RTWc_limit = 0
CCDLc_limit = 0
rwq = 0
CCDLc_limit_alone = 0
WTRc_limit_alone = 0
RTWc_limit_alone = 0
Commands details:
total_CMD = 4154
n_nop = 4154
Read = 0
Write = 0
L2_Alloc = 0
L2_WB = 0
n_act = 0
n_pre = 0
n_ref = 0
n_req = 0
total_req = 0
Dual Bus Interface Util:
issued_total_row = 0
issued_total_col = 0
Row_Bus_Util = 0.000000
CoL_Bus_Util = 0.000000
Either_Row_CoL_Bus_Util = 0.000000
Issued_on_Two_Bus_Simul_Util = 0.000000
issued_two_Eff = -nan
queue_avg = 0.000000
dram_util_bins: 0 0 0 0 0 0 0 0 0 0
dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
mrqq: max=0 avg=0
Memory Partition 24:
Cache L2_bank_048:
MSHR contents
Cache L2_bank_049:
MSHR contents
In Dram Latency Queue (total = 0):
DRAM[24]: 16 bks, busW=16 BL=2 CL=12, tRRD=3 tCCD=1, tRCD=12 tRAS=28 tRP=12 tRC=40
n_cmd=4154 n_nop=4154 n_act=0 n_pre=0 n_ref_event=0 n_req=0 n_rd=0 n_rd_L2_A=0 n_write=0 n_wr_bk=0 bw_util=0
n_activity=0 dram_eff=-nan
bk0: 0a 4154i bk1: 0a 4154i bk2: 0a 4154i bk3: 0a 4154i bk4: 0a 4154i bk5: 0a 4154i bk6: 0a 4154i bk7: 0a 4154i bk8: 0a 4154i bk9: 0a 4154i bk10: 0a 4154i bk11: 0a 4154i bk12: 0a 4154i bk13: 0a 4154i bk14: 0a 4154i bk15: 0a 4154i
------------------------------------------------------------------------
Row_Buffer_Locality = -nan
Row_Buffer_Locality_read = -nan
Row_Buffer_Locality_write = -nan
Bank_Level_Parallism = -nan
Bank_Level_Parallism_Col = -nan
Bank_Level_Parallism_Ready = -nan
write_to_read_ratio_blp_rw_average = -nan
GrpLevelPara = -nan
BW Util details:
bwutil = 0.000000
total_CMD = 4154
util_bw = 0
Wasted_Col = 0
Wasted_Row = 0
Idle = 4154
BW Util Bottlenecks:
RCDc_limit = 0
RCDWRc_limit = 0
WTRc_limit = 0
RTWc_limit = 0
CCDLc_limit = 0
rwq = 0
CCDLc_limit_alone = 0
WTRc_limit_alone = 0
RTWc_limit_alone = 0
Commands details:
total_CMD = 4154
n_nop = 4154
Read = 0
Write = 0
L2_Alloc = 0
L2_WB = 0
n_act = 0
n_pre = 0
n_ref = 0
n_req = 0
total_req = 0
Dual Bus Interface Util:
issued_total_row = 0
issued_total_col = 0
Row_Bus_Util = 0.000000
CoL_Bus_Util = 0.000000
Either_Row_CoL_Bus_Util = 0.000000
Issued_on_Two_Bus_Simul_Util = 0.000000
issued_two_Eff = -nan
queue_avg = 0.000000
dram_util_bins: 0 0 0 0 0 0 0 0 0 0
dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
mrqq: max=0 avg=0
Memory Partition 25:
Cache L2_bank_050:
MSHR contents
Cache L2_bank_051:
MSHR contents
In Dram Latency Queue (total = 0):
DRAM[25]: 16 bks, busW=16 BL=2 CL=12, tRRD=3 tCCD=1, tRCD=12 tRAS=28 tRP=12 tRC=40
n_cmd=4154 n_nop=4154 n_act=0 n_pre=0 n_ref_event=0 n_req=0 n_rd=0 n_rd_L2_A=0 n_write=0 n_wr_bk=0 bw_util=0
n_activity=0 dram_eff=-nan
bk0: 0a 4154i bk1: 0a 4154i bk2: 0a 4154i bk3: 0a 4154i bk4: 0a 4154i bk5: 0a 4154i bk6: 0a 4154i bk7: 0a 4154i bk8: 0a 4154i bk9: 0a 4154i bk10: 0a 4154i bk11: 0a 4154i bk12: 0a 4154i bk13: 0a 4154i bk14: 0a 4154i bk15: 0a 4154i
------------------------------------------------------------------------
Row_Buffer_Locality = -nan
Row_Buffer_Locality_read = -nan
Row_Buffer_Locality_write = -nan
Bank_Level_Parallism = -nan
Bank_Level_Parallism_Col = -nan
Bank_Level_Parallism_Ready = -nan
write_to_read_ratio_blp_rw_average = -nan
GrpLevelPara = -nan
BW Util details:
bwutil = 0.000000
total_CMD = 4154
util_bw = 0
Wasted_Col = 0
Wasted_Row = 0
Idle = 4154
BW Util Bottlenecks:
RCDc_limit = 0
RCDWRc_limit = 0
WTRc_limit = 0
RTWc_limit = 0
CCDLc_limit = 0
rwq = 0
CCDLc_limit_alone = 0
WTRc_limit_alone = 0
RTWc_limit_alone = 0
Commands details:
total_CMD = 4154
n_nop = 4154
Read = 0
Write = 0
L2_Alloc = 0
L2_WB = 0
n_act = 0
n_pre = 0
n_ref = 0
n_req = 0
total_req = 0
Dual Bus Interface Util:
issued_total_row = 0
issued_total_col = 0
Row_Bus_Util = 0.000000
CoL_Bus_Util = 0.000000
Either_Row_CoL_Bus_Util = 0.000000
Issued_on_Two_Bus_Simul_Util = 0.000000
issued_two_Eff = -nan
queue_avg = 0.000000
dram_util_bins: 0 0 0 0 0 0 0 0 0 0
dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
mrqq: max=0 avg=0
Memory Partition 26:
Cache L2_bank_052:
MSHR contents
Cache L2_bank_053:
MSHR contents
In Dram Latency Queue (total = 0):
DRAM[26]: 16 bks, busW=16 BL=2 CL=12, tRRD=3 tCCD=1, tRCD=12 tRAS=28 tRP=12 tRC=40
n_cmd=4154 n_nop=4154 n_act=0 n_pre=0 n_ref_event=0 n_req=0 n_rd=0 n_rd_L2_A=0 n_write=0 n_wr_bk=0 bw_util=0
n_activity=0 dram_eff=-nan
bk0: 0a 4154i bk1: 0a 4154i bk2: 0a 4154i bk3: 0a 4154i bk4: 0a 4154i bk5: 0a 4154i bk6: 0a 4154i bk7: 0a 4154i bk8: 0a 4154i bk9: 0a 4154i bk10: 0a 4154i bk11: 0a 4154i bk12: 0a 4154i bk13: 0a 4154i bk14: 0a 4154i bk15: 0a 4154i
------------------------------------------------------------------------
Row_Buffer_Locality = -nan
Row_Buffer_Locality_read = -nan
Row_Buffer_Locality_write = -nan
Bank_Level_Parallism = -nan
Bank_Level_Parallism_Col = -nan
Bank_Level_Parallism_Ready = -nan
write_to_read_ratio_blp_rw_average = -nan
GrpLevelPara = -nan
BW Util details:
bwutil = 0.000000
total_CMD = 4154
util_bw = 0
Wasted_Col = 0
Wasted_Row = 0
Idle = 4154
BW Util Bottlenecks:
RCDc_limit = 0
RCDWRc_limit = 0
WTRc_limit = 0
RTWc_limit = 0
CCDLc_limit = 0
rwq = 0
CCDLc_limit_alone = 0
WTRc_limit_alone = 0
RTWc_limit_alone = 0
Commands details:
total_CMD = 4154
n_nop = 4154
Read = 0
Write = 0
L2_Alloc = 0
L2_WB = 0
n_act = 0
n_pre = 0
n_ref = 0
n_req = 0
total_req = 0
Dual Bus Interface Util:
issued_total_row = 0
issued_total_col = 0
Row_Bus_Util = 0.000000
CoL_Bus_Util = 0.000000
Either_Row_CoL_Bus_Util = 0.000000
Issued_on_Two_Bus_Simul_Util = 0.000000
issued_two_Eff = -nan
queue_avg = 0.000000
dram_util_bins: 0 0 0 0 0 0 0 0 0 0
dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
mrqq: max=0 avg=0
Memory Partition 27:
Cache L2_bank_054:
MSHR contents
Cache L2_bank_055:
MSHR contents
In Dram Latency Queue (total = 0):
DRAM[27]: 16 bks, busW=16 BL=2 CL=12, tRRD=3 tCCD=1, tRCD=12 tRAS=28 tRP=12 tRC=40
n_cmd=4154 n_nop=4154 n_act=0 n_pre=0 n_ref_event=0 n_req=0 n_rd=0 n_rd_L2_A=0 n_write=0 n_wr_bk=0 bw_util=0
n_activity=0 dram_eff=-nan
bk0: 0a 4154i bk1: 0a 4154i bk2: 0a 4154i bk3: 0a 4154i bk4: 0a 4154i bk5: 0a 4154i bk6: 0a 4154i bk7: 0a 4154i bk8: 0a 4154i bk9: 0a 4154i bk10: 0a 4154i bk11: 0a 4154i bk12: 0a 4154i bk13: 0a 4154i bk14: 0a 4154i bk15: 0a 4154i
------------------------------------------------------------------------
Row_Buffer_Locality = -nan
Row_Buffer_Locality_read = -nan
Row_Buffer_Locality_write = -nan
Bank_Level_Parallism = -nan
Bank_Level_Parallism_Col = -nan
Bank_Level_Parallism_Ready = -nan
write_to_read_ratio_blp_rw_average = -nan
GrpLevelPara = -nan
BW Util details:
bwutil = 0.000000
total_CMD = 4154
util_bw = 0
Wasted_Col = 0
Wasted_Row = 0
Idle = 4154
BW Util Bottlenecks:
RCDc_limit = 0
RCDWRc_limit = 0
WTRc_limit = 0
RTWc_limit = 0
CCDLc_limit = 0
rwq = 0
CCDLc_limit_alone = 0
WTRc_limit_alone = 0
RTWc_limit_alone = 0
Commands details:
total_CMD = 4154
n_nop = 4154
Read = 0
Write = 0
L2_Alloc = 0
L2_WB = 0
n_act = 0
n_pre = 0
n_ref = 0
n_req = 0
total_req = 0
Dual Bus Interface Util:
issued_total_row = 0
issued_total_col = 0
Row_Bus_Util = 0.000000
CoL_Bus_Util = 0.000000
Either_Row_CoL_Bus_Util = 0.000000
Issued_on_Two_Bus_Simul_Util = 0.000000
issued_two_Eff = -nan
queue_avg = 0.000000
dram_util_bins: 0 0 0 0 0 0 0 0 0 0
dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
mrqq: max=0 avg=0
Memory Partition 28:
Cache L2_bank_056:
MSHR contents
Cache L2_bank_057:
MSHR contents
In Dram Latency Queue (total = 0):
DRAM[28]: 16 bks, busW=16 BL=2 CL=12, tRRD=3 tCCD=1, tRCD=12 tRAS=28 tRP=12 tRC=40
n_cmd=4154 n_nop=4154 n_act=0 n_pre=0 n_ref_event=0 n_req=0 n_rd=0 n_rd_L2_A=0 n_write=0 n_wr_bk=0 bw_util=0
n_activity=0 dram_eff=-nan
bk0: 0a 4154i bk1: 0a 4154i bk2: 0a 4154i bk3: 0a 4154i bk4: 0a 4154i bk5: 0a 4154i bk6: 0a 4154i bk7: 0a 4154i bk8: 0a 4154i bk9: 0a 4154i bk10: 0a 4154i bk11: 0a 4154i bk12: 0a 4154i bk13: 0a 4154i bk14: 0a 4154i bk15: 0a 4154i
------------------------------------------------------------------------
Row_Buffer_Locality = -nan
Row_Buffer_Locality_read = -nan
Row_Buffer_Locality_write = -nan
Bank_Level_Parallism = -nan
Bank_Level_Parallism_Col = -nan
Bank_Level_Parallism_Ready = -nan
write_to_read_ratio_blp_rw_average = -nan
GrpLevelPara = -nan
BW Util details:
bwutil = 0.000000
total_CMD = 4154
util_bw = 0
Wasted_Col = 0
Wasted_Row = 0
Idle = 4154
BW Util Bottlenecks:
RCDc_limit = 0
RCDWRc_limit = 0
WTRc_limit = 0
RTWc_limit = 0
CCDLc_limit = 0
rwq = 0
CCDLc_limit_alone = 0
WTRc_limit_alone = 0
RTWc_limit_alone = 0
Commands details:
total_CMD = 4154
n_nop = 4154
Read = 0
Write = 0
L2_Alloc = 0
L2_WB = 0
n_act = 0
n_pre = 0
n_ref = 0
n_req = 0
total_req = 0
Dual Bus Interface Util:
issued_total_row = 0
issued_total_col = 0
Row_Bus_Util = 0.000000
CoL_Bus_Util = 0.000000
Either_Row_CoL_Bus_Util = 0.000000
Issued_on_Two_Bus_Simul_Util = 0.000000
issued_two_Eff = -nan
queue_avg = 0.000000
dram_util_bins: 0 0 0 0 0 0 0 0 0 0
dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
mrqq: max=0 avg=0
Memory Partition 29:
Cache L2_bank_058:
MSHR contents
Cache L2_bank_059:
MSHR contents
In Dram Latency Queue (total = 0):
DRAM[29]: 16 bks, busW=16 BL=2 CL=12, tRRD=3 tCCD=1, tRCD=12 tRAS=28 tRP=12 tRC=40
n_cmd=4154 n_nop=4154 n_act=0 n_pre=0 n_ref_event=0 n_req=0 n_rd=0 n_rd_L2_A=0 n_write=0 n_wr_bk=0 bw_util=0
n_activity=0 dram_eff=-nan
bk0: 0a 4154i bk1: 0a 4154i bk2: 0a 4154i bk3: 0a 4154i bk4: 0a 4154i bk5: 0a 4154i bk6: 0a 4154i bk7: 0a 4154i bk8: 0a 4154i bk9: 0a 4154i bk10: 0a 4154i bk11: 0a 4154i bk12: 0a 4154i bk13: 0a 4154i bk14: 0a 4154i bk15: 0a 4154i
------------------------------------------------------------------------
Row_Buffer_Locality = -nan
Row_Buffer_Locality_read = -nan
Row_Buffer_Locality_write = -nan
Bank_Level_Parallism = -nan
Bank_Level_Parallism_Col = -nan
Bank_Level_Parallism_Ready = -nan
write_to_read_ratio_blp_rw_average = -nan
GrpLevelPara = -nan
BW Util details:
bwutil = 0.000000
total_CMD = 4154
util_bw = 0
Wasted_Col = 0
Wasted_Row = 0
Idle = 4154
BW Util Bottlenecks:
RCDc_limit = 0
RCDWRc_limit = 0
WTRc_limit = 0
RTWc_limit = 0
CCDLc_limit = 0
rwq = 0
CCDLc_limit_alone = 0
WTRc_limit_alone = 0
RTWc_limit_alone = 0
Commands details:
total_CMD = 4154
n_nop = 4154
Read = 0
Write = 0
L2_Alloc = 0
L2_WB = 0
n_act = 0
n_pre = 0
n_ref = 0
n_req = 0
total_req = 0
Dual Bus Interface Util:
issued_total_row = 0
issued_total_col = 0
Row_Bus_Util = 0.000000
CoL_Bus_Util = 0.000000
Either_Row_CoL_Bus_Util = 0.000000
Issued_on_Two_Bus_Simul_Util = 0.000000
issued_two_Eff = -nan
queue_avg = 0.000000
dram_util_bins: 0 0 0 0 0 0 0 0 0 0
dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
mrqq: max=0 avg=0
Memory Partition 30:
Cache L2_bank_060:
MSHR contents
Cache L2_bank_061:
MSHR contents
In Dram Latency Queue (total = 0):
DRAM[30]: 16 bks, busW=16 BL=2 CL=12, tRRD=3 tCCD=1, tRCD=12 tRAS=28 tRP=12 tRC=40
n_cmd=4154 n_nop=4154 n_act=0 n_pre=0 n_ref_event=0 n_req=0 n_rd=0 n_rd_L2_A=0 n_write=0 n_wr_bk=0 bw_util=0
n_activity=0 dram_eff=-nan
bk0: 0a 4154i bk1: 0a 4154i bk2: 0a 4154i bk3: 0a 4154i bk4: 0a 4154i bk5: 0a 4154i bk6: 0a 4154i bk7: 0a 4154i bk8: 0a 4154i bk9: 0a 4154i bk10: 0a 4154i bk11: 0a 4154i bk12: 0a 4154i bk13: 0a 4154i bk14: 0a 4154i bk15: 0a 4154i
------------------------------------------------------------------------
Row_Buffer_Locality = -nan
Row_Buffer_Locality_read = -nan
Row_Buffer_Locality_write = -nan
Bank_Level_Parallism = -nan
Bank_Level_Parallism_Col = -nan
Bank_Level_Parallism_Ready = -nan
write_to_read_ratio_blp_rw_average = -nan
GrpLevelPara = -nan
BW Util details:
bwutil = 0.000000
total_CMD = 4154
util_bw = 0
Wasted_Col = 0
Wasted_Row = 0
Idle = 4154
BW Util Bottlenecks:
RCDc_limit = 0
RCDWRc_limit = 0
WTRc_limit = 0
RTWc_limit = 0
CCDLc_limit = 0
rwq = 0
CCDLc_limit_alone = 0
WTRc_limit_alone = 0
RTWc_limit_alone = 0
Commands details:
total_CMD = 4154
n_nop = 4154
Read = 0
Write = 0
L2_Alloc = 0
L2_WB = 0
n_act = 0
n_pre = 0
n_ref = 0
n_req = 0
total_req = 0
Dual Bus Interface Util:
issued_total_row = 0
issued_total_col = 0
Row_Bus_Util = 0.000000
CoL_Bus_Util = 0.000000
Either_Row_CoL_Bus_Util = 0.000000
Issued_on_Two_Bus_Simul_Util = 0.000000
issued_two_Eff = -nan
queue_avg = 0.000000
dram_util_bins: 0 0 0 0 0 0 0 0 0 0
dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
mrqq: max=0 avg=0
Memory Partition 31:
Cache L2_bank_062:
MSHR contents
Cache L2_bank_063:
MSHR contents
In Dram Latency Queue (total = 0):
DRAM[31]: 16 bks, busW=16 BL=2 CL=12, tRRD=3 tCCD=1, tRCD=12 tRAS=28 tRP=12 tRC=40
n_cmd=4154 n_nop=4154 n_act=0 n_pre=0 n_ref_event=0 n_req=0 n_rd=0 n_rd_L2_A=0 n_write=0 n_wr_bk=0 bw_util=0
n_activity=0 dram_eff=-nan
bk0: 0a 4154i bk1: 0a 4154i bk2: 0a 4154i bk3: 0a 4154i bk4: 0a 4154i bk5: 0a 4154i bk6: 0a 4154i bk7: 0a 4154i bk8: 0a 4154i bk9: 0a 4154i bk10: 0a 4154i bk11: 0a 4154i bk12: 0a 4154i bk13: 0a 4154i bk14: 0a 4154i bk15: 0a 4154i
------------------------------------------------------------------------
Row_Buffer_Locality = -nan
Row_Buffer_Locality_read = -nan
Row_Buffer_Locality_write = -nan
Bank_Level_Parallism = -nan
Bank_Level_Parallism_Col = -nan
Bank_Level_Parallism_Ready = -nan
write_to_read_ratio_blp_rw_average = -nan
GrpLevelPara = -nan
BW Util details:
bwutil = 0.000000
total_CMD = 4154
util_bw = 0
Wasted_Col = 0
Wasted_Row = 0
Idle = 4154
BW Util Bottlenecks:
RCDc_limit = 0
RCDWRc_limit = 0
WTRc_limit = 0
RTWc_limit = 0
CCDLc_limit = 0
rwq = 0
CCDLc_limit_alone = 0
WTRc_limit_alone = 0
RTWc_limit_alone = 0
Commands details:
total_CMD = 4154
n_nop = 4154
Read = 0
Write = 0
L2_Alloc = 0
L2_WB = 0
n_act = 0
n_pre = 0
n_ref = 0
n_req = 0
total_req = 0
Dual Bus Interface Util:
issued_total_row = 0
issued_total_col = 0
Row_Bus_Util = 0.000000
CoL_Bus_Util = 0.000000
Either_Row_CoL_Bus_Util = 0.000000
Issued_on_Two_Bus_Simul_Util = 0.000000
issued_two_Eff = -nan
queue_avg = 0.000000
dram_util_bins: 0 0 0 0 0 0 0 0 0 0
dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
mrqq: max=0 avg=0
========= L2 cache stats =========
L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[16]: Access = 8, Miss = 0, Miss_rate = 0.000, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[18]: Access = 8, Miss = 0, Miss_rate = 0.000, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[20]: Access = 8, Miss = 0, Miss_rate = 0.000, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[22]: Access = 8, Miss = 0, Miss_rate = 0.000, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[24]: Access = 8, Miss = 0, Miss_rate = 0.000, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[26]: Access = 8, Miss = 0, Miss_rate = 0.000, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[28]: Access = 16, Miss = 0, Miss_rate = 0.000, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[29]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[30]: Access = 10, Miss = 0, Miss_rate = 0.000, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[31]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[32]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[33]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[34]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[35]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[36]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[37]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[38]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[39]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[40]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[41]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[42]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[43]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[44]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[45]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[46]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[47]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[48]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[49]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[50]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[51]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[52]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[53]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[54]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[55]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[56]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[57]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[58]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[59]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[60]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[61]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[62]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[63]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L2_total_cache_accesses = 74
L2_total_cache_misses = 0
L2_total_cache_miss_rate = 0.0000
L2_total_cache_pending_hits = 0
L2_total_cache_reservation_fails = 0
L2_total_cache_breakdown:
L2_cache_stats_breakdown[GLOBAL_ACC_R][HIT] = 13
L2_cache_stats_breakdown[GLOBAL_ACC_R][HIT_RESERVED] = 0
L2_cache_stats_breakdown[GLOBAL_ACC_R][MISS] = 0
L2_cache_stats_breakdown[GLOBAL_ACC_R][RESERVATION_FAIL] = 0
L2_cache_stats_breakdown[GLOBAL_ACC_R][SECTOR_MISS] = 0
L2_cache_stats_breakdown[LOCAL_ACC_R][HIT] = 0
L2_cache_stats_breakdown[LOCAL_ACC_R][HIT_RESERVED] = 0
L2_cache_stats_breakdown[LOCAL_ACC_R][MISS] = 0
L2_cache_stats_breakdown[LOCAL_ACC_R][RESERVATION_FAIL] = 0
L2_cache_stats_breakdown[LOCAL_ACC_R][SECTOR_MISS] = 0
L2_cache_stats_breakdown[CONST_ACC_R][HIT] = 0
L2_cache_stats_breakdown[CONST_ACC_R][HIT_RESERVED] = 0
L2_cache_stats_breakdown[CONST_ACC_R][MISS] = 0
L2_cache_stats_breakdown[CONST_ACC_R][RESERVATION_FAIL] = 0
L2_cache_stats_breakdown[CONST_ACC_R][SECTOR_MISS] = 0
L2_cache_stats_breakdown[TEXTURE_ACC_R][HIT] = 0
L2_cache_stats_breakdown[TEXTURE_ACC_R][HIT_RESERVED] = 0
L2_cache_stats_breakdown[TEXTURE_ACC_R][MISS] = 0
L2_cache_stats_breakdown[TEXTURE_ACC_R][RESERVATION_FAIL] = 0
L2_cache_stats_breakdown[TEXTURE_ACC_R][SECTOR_MISS] = 0
L2_cache_stats_breakdown[GLOBAL_ACC_W][HIT] = 61
L2_cache_stats_breakdown[GLOBAL_ACC_W][HIT_RESERVED] = 0
L2_cache_stats_breakdown[GLOBAL_ACC_W][MISS] = 0
L2_cache_stats_breakdown[GLOBAL_ACC_W][RESERVATION_FAIL] = 0
L2_cache_stats_breakdown[GLOBAL_ACC_W][SECTOR_MISS] = 0
L2_cache_stats_breakdown[LOCAL_ACC_W][HIT] = 0
L2_cache_stats_breakdown[LOCAL_ACC_W][HIT_RESERVED] = 0
L2_cache_stats_breakdown[LOCAL_ACC_W][MISS] = 0
L2_cache_stats_breakdown[LOCAL_ACC_W][RESERVATION_FAIL] = 0
L2_cache_stats_breakdown[LOCAL_ACC_W][SECTOR_MISS] = 0
L2_cache_stats_breakdown[L1_WRBK_ACC][HIT] = 0
L2_cache_stats_breakdown[L1_WRBK_ACC][HIT_RESERVED] = 0
L2_cache_stats_breakdown[L1_WRBK_ACC][MISS] = 0
L2_cache_stats_breakdown[L1_WRBK_ACC][RESERVATION_FAIL] = 0
L2_cache_stats_breakdown[L1_WRBK_ACC][SECTOR_MISS] = 0
L2_cache_stats_breakdown[L2_WRBK_ACC][HIT] = 0
L2_cache_stats_breakdown[L2_WRBK_ACC][HIT_RESERVED] = 0
L2_cache_stats_breakdown[L2_WRBK_ACC][MISS] = 0
L2_cache_stats_breakdown[L2_WRBK_ACC][RESERVATION_FAIL] = 0
L2_cache_stats_breakdown[L2_WRBK_ACC][SECTOR_MISS] = 0
L2_cache_stats_breakdown[INST_ACC_R][HIT] = 0
L2_cache_stats_breakdown[INST_ACC_R][HIT_RESERVED] = 0
L2_cache_stats_breakdown[INST_ACC_R][MISS] = 0
L2_cache_stats_breakdown[INST_ACC_R][RESERVATION_FAIL] = 0
L2_cache_stats_breakdown[INST_ACC_R][SECTOR_MISS] = 0
L2_cache_stats_breakdown[L1_WR_ALLOC_R][HIT] = 0
L2_cache_stats_breakdown[L1_WR_ALLOC_R][HIT_RESERVED] = 0
L2_cache_stats_breakdown[L1_WR_ALLOC_R][MISS] = 0
L2_cache_stats_breakdown[L1_WR_ALLOC_R][RESERVATION_FAIL] = 0
L2_cache_stats_breakdown[L1_WR_ALLOC_R][SECTOR_MISS] = 0
L2_cache_stats_breakdown[L2_WR_ALLOC_R][HIT] = 0
L2_cache_stats_breakdown[L2_WR_ALLOC_R][HIT_RESERVED] = 0
L2_cache_stats_breakdown[L2_WR_ALLOC_R][MISS] = 0
L2_cache_stats_breakdown[L2_WR_ALLOC_R][RESERVATION_FAIL] = 0
L2_cache_stats_breakdown[L2_WR_ALLOC_R][SECTOR_MISS] = 0
L2_cache_stats_breakdown[GLOBAL_ACC_R][TOTAL_ACCESS] = 13
L2_cache_stats_breakdown[GLOBAL_ACC_W][TOTAL_ACCESS] = 61
L2_total_cache_reservation_fail_breakdown:
L2_cache_data_port_util = 0.000
L2_cache_fill_port_util = 0.000
icnt_total_pkts_mem_to_simt=74
icnt_total_pkts_simt_to_mem=74
LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
----------------------------Interconnect-DETAILS--------------------------------
Req_Network_injected_packets_num = 74
Req_Network_cycles = 5533
Req_Network_injected_packets_per_cycle = 0.0134
Req_Network_conflicts_per_cycle = 0.0000
Req_Network_conflicts_per_cycle_util = 0.0000
Req_Bank_Level_Parallism = 1.8500
Req_Network_in_buffer_full_per_cycle = 0.0000
Req_Network_in_buffer_avg_util = 0.0000
Req_Network_out_buffer_full_per_cycle = 0.0000
Req_Network_out_buffer_avg_util = 0.0002
Reply_Network_injected_packets_num = 74
Reply_Network_cycles = 5533
Reply_Network_injected_packets_per_cycle = 0.0134
Reply_Network_conflicts_per_cycle = 0.0000
Reply_Network_conflicts_per_cycle_util = 0.0000
Reply_Bank_Level_Parallism = 1.8500
Reply_Network_in_buffer_full_per_cycle = 0.0000
Reply_Network_in_buffer_avg_util = 0.0000
Reply_Network_out_buffer_full_per_cycle = 0.0000
Reply_Network_out_buffer_avg_util = 0.0002
----------------------------END-of-Interconnect-DETAILS-------------------------
gpgpu_simulation_time = 0 days, 0 hrs, 0 min, 3 sec (3 sec)
gpgpu_simulation_rate = 1763 (inst/sec)
gpgpu_simulation_rate = 1844 (cycle/sec)
gpgpu_silicon_slowdown = 613882x
[{ 'id' : 0, 'clk' : 277 }
,{ 'id' : 1, 'clk' : 277 }
,{ 'id' : 2, 'clk' : 277 }
,{ 'id' : 3, 'clk' : 277 }
,{ 'id' : 4, 'clk' : 277 }
,{ 'id' : 5, 'clk' : 277 }
,{ 'id' : 6, 'clk' : 277 }
,{ 'id' : 7, 'clk' : 277 }
,{ 'id' : 8, 'clk' : 277 }
,{ 'id' : 9, 'clk' : 277 }
,{ 'id' : 10, 'clk' : 277 }
,{ 'id' : 11, 'clk' : 277 }
,{ 'id' : 12, 'clk' : 277 }
,{ 'id' : 13, 'clk' : 277 }
,{ 'id' : 14, 'clk' : 277 }
,{ 'id' : 15, 'clk' : 277 }
,{ 'id' : 16, 'clk' : 277 }
,{ 'id' : 17, 'clk' : 277 }
,{ 'id' : 18, 'clk' : 277 }
,{ 'id' : 19, 'clk' : 277 }
,{ 'id' : 20, 'clk' : 277 }
,{ 'id' : 21, 'clk' : 277 }
,{ 'id' : 22, 'clk' : 277 }
,{ 'id' : 23, 'clk' : 277 }
,{ 'id' : 24, 'clk' : 277 }
,{ 'id' : 25, 'clk' : 277 }
,{ 'id' : 26, 'clk' : 277 }
,{ 'id' : 27, 'clk' : 277 }
,{ 'id' : 28, 'clk' : 277 }
,{ 'id' : 29, 'clk' : 277 }
,{ 'id' : 30, 'clk' : 277 }
,{ 'id' : 31, 'clk' : 277 }
,{ 'id' : 32, 'clk' : 281 }
,{ 'id' : 33, 'clk' : 281 }
,{ 'id' : 34, 'clk' : 281 }
,{ 'id' : 35, 'clk' : 281 }
,{ 'id' : 36, 'clk' : 281 }
,{ 'id' : 37, 'clk' : 281 }
,{ 'id' : 38, 'clk' : 281 }
,{ 'id' : 39, 'clk' : 281 }
,{ 'id' : 40, 'clk' : 281 }
,{ 'id' : 41, 'clk' : 281 }
,{ 'id' : 42, 'clk' : 281 }
,{ 'id' : 43, 'clk' : 281 }
,{ 'id' : 44, 'clk' : 281 }
,{ 'id' : 45, 'clk' : 281 }
,{ 'id' : 46, 'clk' : 281 }
,{ 'id' : 47, 'clk' : 281 }
,{ 'id' : 48, 'clk' : 281 }
,{ 'id' : 49, 'clk' : 281 }
,{ 'id' : 50, 'clk' : 281 }
,{ 'id' : 51, 'clk' : 281 }
,{ 'id' : 52, 'clk' : 281 }
,{ 'id' : 53, 'clk' : 281 }
,{ 'id' : 54, 'clk' : 281 }
,{ 'id' : 55, 'clk' : 281 }
,{ 'id' : 56, 'clk' : 281 }
,{ 'id' : 57, 'clk' : 281 }
,{ 'id' : 58, 'clk' : 281 }
,{ 'id' : 59, 'clk' : 281 }
,{ 'id' : 60, 'clk' : 281 }
,{ 'id' : 61, 'clk' : 281 }
,{ 'id' : 62, 'clk' : 281 }
,{ 'id' : 63, 'clk' : 281 }
,{ 'id' : 64, 'clk' : 277 }
,{ 'id' : 65, 'clk' : 277 }
,{ 'id' : 66, 'clk' : 277 }
,{ 'id' : 67, 'clk' : 277 }
,{ 'id' : 68, 'clk' : 277 }
,{ 'id' : 69, 'clk' : 277 }
,{ 'id' : 70, 'clk' : 277 }
,{ 'id' : 71, 'clk' : 277 }
,{ 'id' : 72, 'clk' : 277 }
,{ 'id' : 73, 'clk' : 277 }
,{ 'id' : 74, 'clk' : 277 }
,{ 'id' : 75, 'clk' : 277 }
,{ 'id' : 76, 'clk' : 277 }
,{ 'id' : 77, 'clk' : 277 }
,{ 'id' : 78, 'clk' : 277 }
,{ 'id' : 79, 'clk' : 277 }
,{ 'id' : 80, 'clk' : 277 }
,{ 'id' : 81, 'clk' : 277 }
,{ 'id' : 82, 'clk' : 277 }
,{ 'id' : 83, 'clk' : 277 }
,{ 'id' : 84, 'clk' : 277 }
,{ 'id' : 85, 'clk' : 277 }
,{ 'id' : 86, 'clk' : 277 }
,{ 'id' : 87, 'clk' : 277 }
,{ 'id' : 88, 'clk' : 277 }
,{ 'id' : 89, 'clk' : 277 }
,{ 'id' : 90, 'clk' : 277 }
,{ 'id' : 91, 'clk' : 277 }
,{ 'id' : 92, 'clk' : 277 }
,{ 'id' : 93, 'clk' : 277 }
,{ 'id' : 94, 'clk' : 277 }
,{ 'id' : 95, 'clk' : 277 }
,{ 'id' : 96, 'clk' : 278 }
,{ 'id' : 97, 'clk' : 278 }
,{ 'id' : 98, 'clk' : 278 }
,{ 'id' : 99, 'clk' : 278 }
,{ 'id' : 100, 'clk' : 278 }
,{ 'id' : 101, 'clk' : 278 }
,{ 'id' : 102, 'clk' : 278 }
,{ 'id' : 103, 'clk' : 278 }
,{ 'id' : 104, 'clk' : 278 }
,{ 'id' : 105, 'clk' : 278 }
,{ 'id' : 106, 'clk' : 278 }
,{ 'id' : 107, 'clk' : 278 }
,{ 'id' : 108, 'clk' : 278 }
,{ 'id' : 109, 'clk' : 278 }
,{ 'id' : 110, 'clk' : 278 }
,{ 'id' : 111, 'clk' : 278 }
,{ 'id' : 112, 'clk' : 278 }
,{ 'id' : 113, 'clk' : 278 }
,{ 'id' : 114, 'clk' : 278 }
,{ 'id' : 115, 'clk' : 278 }
,{ 'id' : 116, 'clk' : 278 }
,{ 'id' : 117, 'clk' : 278 }
,{ 'id' : 118, 'clk' : 278 }
,{ 'id' : 119, 'clk' : 278 }
,{ 'id' : 120, 'clk' : 278 }
,{ 'id' : 121, 'clk' : 278 }
,{ 'id' : 122, 'clk' : 278 }
,{ 'id' : 123, 'clk' : 278 }
,{ 'id' : 124, 'clk' : 278 }
,{ 'id' : 125, 'clk' : 278 }
,{ 'id' : 126, 'clk' : 278 }
,{ 'id' : 127, 'clk' : 278 }
,{ 'id' : 128, 'clk' : 17 }
,{ 'id' : 129, 'clk' : 17 }
,{ 'id' : 130, 'clk' : 17 }
,{ 'id' : 131, 'clk' : 17 }
,{ 'id' : 132, 'clk' : 17 }
,{ 'id' : 133, 'clk' : 17 }
,{ 'id' : 134, 'clk' : 17 }
,{ 'id' : 135, 'clk' : 17 }
,{ 'id' : 136, 'clk' : 17 }
,{ 'id' : 137, 'clk' : 17 }
,{ 'id' : 138, 'clk' : 17 }
,{ 'id' : 139, 'clk' : 17 }
,{ 'id' : 140, 'clk' : 17 }
,{ 'id' : 141, 'clk' : 17 }
,{ 'id' : 142, 'clk' : 17 }
,{ 'id' : 143, 'clk' : 17 }
,{ 'id' : 144, 'clk' : 17 }
,{ 'id' : 145, 'clk' : 17 }
,{ 'id' : 146, 'clk' : 17 }
,{ 'id' : 147, 'clk' : 17 }
,{ 'id' : 148, 'clk' : 17 }
,{ 'id' : 149, 'clk' : 17 }
,{ 'id' : 150, 'clk' : 17 }
,{ 'id' : 151, 'clk' : 17 }
,{ 'id' : 152, 'clk' : 17 }
,{ 'id' : 153, 'clk' : 17 }
,{ 'id' : 154, 'clk' : 17 }
,{ 'id' : 155, 'clk' : 17 }
,{ 'id' : 156, 'clk' : 17 }
,{ 'id' : 157, 'clk' : 17 }
,{ 'id' : 158, 'clk' : 17 }
,{ 'id' : 159, 'clk' : 17 }
,{ 'id' : 160, 'clk' : 17 }
,{ 'id' : 161, 'clk' : 17 }
,{ 'id' : 162, 'clk' : 17 }
,{ 'id' : 163, 'clk' : 17 }
,{ 'id' : 164, 'clk' : 17 }
,{ 'id' : 165, 'clk' : 17 }
,{ 'id' : 166, 'clk' : 17 }
,{ 'id' : 167, 'clk' : 17 }
,{ 'id' : 168, 'clk' : 17 }
,{ 'id' : 169, 'clk' : 17 }
,{ 'id' : 170, 'clk' : 17 }
,{ 'id' : 171, 'clk' : 17 }
,{ 'id' : 172, 'clk' : 17 }
,{ 'id' : 173, 'clk' : 17 }
,{ 'id' : 174, 'clk' : 17 }
,{ 'id' : 175, 'clk' : 17 }
,{ 'id' : 176, 'clk' : 17 }
,{ 'id' : 177, 'clk' : 17 }
,{ 'id' : 178, 'clk' : 17 }
,{ 'id' : 179, 'clk' : 17 }
,{ 'id' : 180, 'clk' : 17 }
,{ 'id' : 181, 'clk' : 17 }
,{ 'id' : 182, 'clk' : 17 }
,{ 'id' : 183, 'clk' : 17 }
,{ 'id' : 184, 'clk' : 17 }
,{ 'id' : 185, 'clk' : 17 }
,{ 'id' : 186, 'clk' : 17 }
,{ 'id' : 187, 'clk' : 17 }
,{ 'id' : 188, 'clk' : 17 }
,{ 'id' : 189, 'clk' : 17 }
,{ 'id' : 190, 'clk' : 17 }
,{ 'id' : 191, 'clk' : 17 }
]GPGPU-Sim: *** exit detected ***
我们使用 GPU 的模拟器肯定不只是为了只是单纯的在 CPU 上跑起 GPU 程序，更重要的是希望按照自己的需要调整 GPU 的参数，预测应用的运行效果。而想要真实、客观的评估我们调整的效果，单一的评测基准是不够的，我们需要在模拟器上运行的是整套的评测集合。
GPGPU-Sim 官方提供了一个仿真程序包，提供了一些常用测试集以及对应的安装脚本。不幸的是，该仓库已经很久没有更新，默认的配置还是基于 [email protected],cuda@4 左右的版本的，很多代码甚至要追溯到数十年前。因此我将在后续的博客中分别介绍其中一些测试集以及使用 GPGPU-Sim 仿真姿势。
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