单周期CPU设计

`timescale 1ns / 1ps
module SingleCPU(
	input CLK,	//时钟信号
	input Reset,	//置零信号
	output[31:0] CurPC,	//当前指令地址
	output[31:0] newaddress,	//下一个指令地址
	output[31:0] instcode,	//rs,rt寄存器所在指令
	output[31:0] Reg1Out,	//寄存器组rs寄存器的值
	output[31:0] Reg2Out,	//寄存器组rt寄存器的值
	output[31:0] ALU_Out,	//ALU的result输出值
	output[31:0] WriteData	//DB总线值
);
	wire ExtSel;	//位扩展信号，1为符号扩展，0为0扩展
	wire PCWre;	//PC工作信号，0不更改，1更改
	wire InsMemRW;	//指令寄存器信号，0为写，1为读
	wire RegDst;	//指令读取时判断是rt还是rd进入寄存器组的写数据端，0为rt，1为rd
	wire RegWre;	//寄存器组是否需要写功能，0为无写功能，1为些功能
	wire[2:0] ALUOp;	//ALU8种运算功能选择
	wire[1:0] PCSrc;	//PC正常+4还是要跳转，0为正常+4，1为跳转
	wire ALUSrcA;	//寄存器组Data1的输出，0为寄存器本身输出，1为指令码的最后16位立即数
	wire ALUSrcB;	//寄存器组Data2的输出，0位本身的输出，1为扩展后的立即数
	wire RD;	//读数据存储器功能，0时读取
	wire WR;	//写数据存储器功能，1时写
	wire DBDataSrc;	//决定将什么数据传入寄存器组Write Data端，0为ALU结果，1为存储器
	wire[4:0] WriteRegAddr;	//寄存器组Write Reg输入端
	wire[31:0] ALU_Input_A;	//ALU的A输入端
	wire[31:0] ALU_Input_B;	//ALU的B输入端
	wire zero;	//ALU的zero输出
	wire sign;	//ALU的sign输出
	wire[31:0] MemOut;	//存储器的输出
	wire[31:0] Ext_Imm;	//位扩展后的立即数
	wire[31:0] CurPC4=CurPC+4;
	assign newaddress=	(PCSrc==2'b01)?{CurPC4[31:28],instcode[25:0],2'b00}:
						(PCSrc==2'b10)?CurPC4+(Ext_Imm<<2):CurPC4;
	PC pc(CLK,Reset,PCWre,newaddress,CurPC);
	ALU alu(ALU_Input_A,ALU_Input_B,ALUOp,ALU_Out,zero,sign);
	DataMemory dm(ALU_Out,CLK,RD,WR,Reg2Out,MemOut);
	SignZeroExtend sze(instcode[15:0],ExtSel,Ext_Imm);
	Multiplexer5 mux21R(RegDst,instcode[20:16],instcode[15:11],WriteRegAddr);
	Multiplexer32 mux21A(ALUSrcA,Reg1Out,{27'b000000000000000000000000000,instcode[10:6]},ALU_Input_A);
	Multiplexer32 mux21B(ALUSrcB,Reg2Out,Ext_Imm,ALU_Input_B);
	Multiplexer32 mux21RW(DBDataSrc,ALU_Out,MemOut,WriteData);
	RegisterFile rf(RegWre,CLK,instcode[25:21],instcode[20:16],WriteRegAddr,WriteData,Reg1Out,Reg2Out);
	ControlUnit cu(ExtSel,PCWre,InsMemRW,RegDst,RegWre,ALUOp,PCSrc,ALUSrcA,ALUSrcB,RD,WR,DBDataSrc,instcode[31:26],zero,sign);
	InstructionMemory im(CurPC,InsMemRW,instcode);
endmodule

`timescale 1ns / 1ps
module ControlUnit(
	output ExtSel,
	output PCWre,
	output InsMemRW,
	output RegDst,
	output RegWre,
	output[2:0] ALUOp,
	output[1:0] PCSrc,
	output ALUSrcA,
	output ALUSrcB,
	output mRD,
	output mWR,
	output DBDataSrc,
	input[5:0] op,
	input zero,
	input sign
);
	parameter ADD=	6'b000000;
	parameter SUB=	6'b000001;
	parameter ADDIU=	6'b000010;
	parameter ANDI=	6'b010000;
	parameter AND=	6'b010001;
	parameter ORI=	6'b010010;
	parameter OR=	6'b010011;
	parameter SLL=	6'b011000;
	parameter SLTI=	6'b011100;
	parameter SW=	6'b100110;
	parameter LW=	6'b100111;
	parameter BEQ=	6'b110000;
	parameter BNE=	6'b110001;
	parameter BLTZ=	6'b110010;
	parameter J=	6'b111000;
	parameter HALT=	6'b111111;
	parameter _ADD=	3'b000;
	parameter _SUB=	3'b001;
	parameter _SLL=	3'b010;
	parameter _OR=	3'b011;
	parameter _AND=	3'b100;
	parameter _SLTU=	3'b101;
	parameter _SLT=	3'b110;
	parameter _XOR=	3'b111;

	assign PCWre=	op!=HALT;
	assign ALUSrcA=	op==SLL;
	assign ALUSrcB=	op==ADDIU||op==ANDI||op==ORI||op==SLTI||op==SW||op==LW;
	assign DBDataSrc=	op==LW;
	assign RegWre=	op!=BEQ&&op!=BNE&&op!=BLTZ&&op!=SW&&op!=HALT;
	assign InsMemRW=	0;
	assign mRD=	op==LW;
	assign mWR=	op==SW;
	assign RegDst=	op!=ADDIU&&op!=ANDI&&op!=ORI&&op!=SLTI&&op!=LW;
	assign ExtSel=	op!=ANDI&&op!=ORI;
	assign PCSrc[0]=	op==J;
	assign PCSrc[1]=	op==BEQ&&zero==1||op==BNE&&zero==0||op==BLTZ&&sign==1;
	assign ALUOp=	op==SUB||op==BNE||op==BEQ||op==BLTZ?_SUB:
					op==SLL?_SLL:
					op==ORI||op==OR?_OR:
					op==ANDI||op==AND?_AND:
					op==SLTI?_SLT:_ADD;
endmodule

`timescale 1ns / 1ps
module ALU(
	input[31:0] A,	//输入A
	input[31:0] B,	//输入B
	input[2:0] ALUOp,	//ALU操作控制
	output reg[31:0] result,	//ALU运算结果
	output zero,	//运算结果result的标志，result为0输出1，否则输出0
	output sign	//运算结果result的正负性（有符号数的情况），result为负数输出1，否则输出0
);
	parameter _ADD=	3'b000;
	parameter _SUB=	3'b001;
	parameter _SLL=	3'b010;
	parameter _OR=	3'b011;
	parameter _AND=	3'b100;
	parameter _SLTU=	3'b101;
	parameter _SLT=	3'b110;
	parameter _XOR=	3'b111;

	assign zero=	result==0;
	assign sign=	result[31];

	always@(*)begin	//进行ALU计算
		case(ALUOp)	//进行运算
		_ADD:	result=	A+B;  //加法
		_SUB:	result=	A-B;  //减法
		_SLL:	result=	B<<A;  //B左移A位
		_OR:	result=	A|B;  //或
		_AND:	result=	A&B;  //与
		_SLTU:	result=	A<B;  //比较A<B不带符号
		_SLT:	result=	A[31]!=B[31]?A[31]>B[31]:A<B;	//比较A<B带符号
		_XOR:	result=	A^B;	//异或
		default:	result=	0;
		endcase
	end
endmodule

`timescale 1ns / 1ps
module DataMemory(
	input[31:0] DAddr,
	input CLK,
	input mRD,
	input mWR,
	input[31:0] DataIn,
	output reg[31:0] DataOut
);
	reg[7:0] dataMemory [255:0];
	always@(mRD or DAddr)begin
		if(mRD)begin
			DataOut[7:0]=	dataMemory[DAddr+3];
			DataOut[15:8]=	dataMemory[DAddr+2];
			DataOut[23:16]=	dataMemory[DAddr+1];
			DataOut[31:24]=	dataMemory[DAddr];
		end
	end
	always@(negedge CLK)begin	//总是在时钟下降沿到来时触发
		if(mWR)begin
			dataMemory[DAddr+3]<=	DataIn[7:0];
			dataMemory[DAddr+2]<=	DataIn[15:8];
			dataMemory[DAddr+1]<=	DataIn[23:16];
			dataMemory[DAddr]<=	DataIn[31:24];
		end
	end
endmodule

`timescale 1ns / 1ps
module InstructionMemory(
	input[31:0] IAddr,
	input RW,
	output reg[31:0] IDataOut
);
	reg[7:0] InstMemory[255:0];
	initial begin	//此处为绝对地址，注意斜杠方向
		$readmemb("C:/Users/wukan/Documents/VIVADO/SingleCPU/input.txt",InstMemory);
	end
	always@(IAddr or RW)begin
		if(RW==0)begin
			IDataOut=	{InstMemory[IAddr],InstMemory[IAddr+1],InstMemory[IAddr+2],InstMemory[IAddr+3]};
		end
	end
endmodule

`timescale 1ns / 1ps
module Multiplexer32(
	input Select,
	input[31:0] DataIn1,
	input[31:0] DataIn2,
	output[31:0] DataOut
);
	assign DataOut=	Select?DataIn2:DataIn1;
endmodule

`timescale 1ns / 1ps
module Multiplexer5(
	input Select,
	input[4:0] DataIn1,
	input[4:0] DataIn2,
	output[4:0] DataOut
);
	assign DataOut=	Select?DataIn2:DataIn1;
endmodule

`timescale 1ns / 1ps
module PC(
	input CLK,
	input Reset,
	input PCWre,
	input[31:0] newAddress,
	output reg[31:0] PCAddr
);
	initial begin
		PCAddr=	0;
	end
	always@(posedge CLK or negedge Reset)begin
		if(Reset==0)begin
			PCAddr=	0;
		end
		else if(PCWre)begin
			PCAddr=	newAddress;
		end
	end
endmodule

`timescale 1ns / 1ps
module RegisterFile(
	input WE,
	input CLK,
	input[4:0] ReadReg1,
	input[4:0] ReadReg2,
	input[4:0] WriteReg,
	input[31:0] WriteData,
	output[31:0] ReadData1,
	output[31:0] ReadData2
);
	reg[31:0] registers[0:31];
	integer i;
	initial begin	//初始时，将32个寄存器全部赋值为0
		for(i=0; i<32; i=i+1)registers[i]<=	0;
	end
	assign ReadData1=	ReadReg1?registers[ReadReg1]:0;
	assign ReadData2=	ReadReg2?registers[ReadReg2]:0;
	always@(negedge CLK)begin
		if(WriteReg&&WE)begin
			registers[WriteReg]=	WriteData;
		end
	end
endmodule

`timescale 1ns / 1ps
module SignZeroExtend(
	input[15:0] immediate,
	input ExtSel,
	output[31:0] extendImmediate
);
	assign extendImmediate=	{ExtSel&&immediate[15]?16'hffff:16'h0000,immediate};
endmodule

`timescale 1ns / 1ps
module Sim;
	reg CLK;	//时钟信号
	reg Reset;	//置零信号
	SingleCPU scpu(CLK,Reset);
	initial begin
		CLK=	0;
		Reset=	0;	//刚开始设置pc为0

		#50;	//等待Reset完成
		CLK=	!CLK;	//下降沿，使PC先清零
		#50;
		Reset=	1;	//清除保持信号
	  	forever #50 begin	//产生时钟信号，周期为50s
			CLK=	!CLK;
		end
	end
endmodule

`timescale 1ns / 1ps
module Basys3(
	input CLK,
	input[1:0] SW,	//选择输出信号
	input Reset,	//重置按钮
	input Button,	//单脉冲
	output reg[3:0] AN,	//数码管位选择信号
	output[7:0] Out	//数码管输入信号
);
	parameter T1MS=	100000;
	reg[16:0] showCounter;
	wire[31:0] ALU_Out;	//ALU的result输出值
	wire[31:0] CurPC;
	wire[31:0] WriteData;	//DB总线值
	wire[31:0] Reg1Out;	//寄存器组rs寄存器的值
	wire[31:0] Reg2Out;	//寄存器组rt寄存器的值
	wire[31:0] instcode;
	wire myCLK;
	reg[3:0] store;	//记录当前要显示位的值
	wire[31:0] newAddress;

	SingleCPU scpu(myCLK,Reset,CurPC,newAddress,instcode,Reg1Out,Reg2Out,ALU_Out,WriteData);

	Debounce debounce(CLK,Button,myCLK);

	initial begin
		showCounter<=	0;
		AN<=	4'b0111;
	end
	always@(posedge CLK)
		begin
		if(Reset==0)begin
		  showCounter<=	0;
		  AN<=	4'b0000;
		end else begin
			showCounter<=	showCounter+1;
			if(showCounter==T1MS)
				begin
					showCounter<=	0;
					case(AN)
						4'b1110:	begin
							AN<=	4'b1101;
						end
						4'b1101:	begin
							AN<=	4'b1011;
						end
						4'b1011:	begin
							AN<=	4'b0111;
						end
						4'b0111:	begin
							AN<=	4'b1110;
						end
						4'b0000:	begin
							AN<=	4'b0111;
					   end
					endcase
				end
			end
		end
	SegLED led(store,Reset,Out);
	always@(myCLK)begin
	   case(AN)
			4'b1110:	begin
				case(SW)
					2'b00:	store<=	newAddress[3:0];
					2'b01:	store<=	Reg1Out[3:0];
					2'b10:	store<=	Reg2Out[3:0];
					2'b11:	store<=	WriteData[3:0];
				endcase
			end
			4'b1101:	begin
				case(SW)
					2'b00:	store<=	newAddress[7:4];
					2'b01:	store<=	Reg1Out[7:4];
					2'b10:	store<=	Reg2Out[7:4];
					2'b11:	store<=	WriteData[7:4];
				endcase
			end
			4'b1011:	begin
				case(SW)
					2'b00:	store<=	CurPC[3:0];
					2'b01:	store<=	instcode[24:21];
					2'b10:	store<=	instcode[19:16];
					2'b11:	store<=	ALU_Out[3:0];
				endcase
			end
			4'b0111 : begin
				case(SW)
					2'b00:	store<=	CurPC[7:4];
					2'b01:	store<=	{3'b000,instcode[25]};
					2'b10:	store<=	{3'b000,instcode[20]};
					2'b11:	store<=	ALU_Out[7:4];
				endcase
			end
		endcase
	end
endmodule

`timescale 1ns / 1ps
module Debounce(clk,key_in,key_out);
	parameter SAMPLE_TIME=	5000;
	input clk;
	input key_in;
	output key_out;
	reg[21:0] count_low;
	reg[21:0] count_high;
	reg key_out_reg;

	always@(posedge clk)begin
		count_low<=	key_in?0:count_low+1;
		count_high<=	key_in?0:count_high+1;
		if(count_high == SAMPLE_TIME)
			key_out_reg<=	1;
		else if(count_low == SAMPLE_TIME)
			key_out_reg<=	0;
	end
	assign key_out=!key_out_reg;
endmodule

`timescale 1ns / 1ps
module SegLED(
	input[3:0] Store,
	input Reset,
	output reg[7:0] Out
);
	always@(Store or Reset)begin
		if(Reset==0)begin
			Out=	8'b11111110;
		end
		else begin
			case(Store)
				4'b0000:	Out=	8'b00000011;	//0
				4'b0001:	Out=	8'b10011111;	//1
				4'b0010:	Out=	8'b00100101;	//2
				4'b0011:	Out=	8'b00001101;	//3
				4'b0100:	Out=	8'b10011001;	//4
				4'b0101:	Out=	8'b01001001;	//5
				4'b0110:	Out=	8'b01000001;	//6
				4'b0111:	Out=	8'b00011111;	//7
				4'b1000:	Out=	8'b00000001;	//8
				4'b1001:	Out=	8'b00001001;	//9
				4'b1010:	Out=	8'b00010001;	//A
				4'b1011:	Out=	8'b11000001;	//b
				4'b1100:	Out=	8'b01100011;	//C
				4'b1101:	Out=	8'b10000101;	//d
				4'b1110:	Out=	8'b01100001;	//E
				4'b1111:	Out=	8'b01110001;	//F
				default:	Out=	8'b00000000;	//all light
			endcase
		end
	end
endmodule